1. IWORID 2002 - P.Randaccio Medipix2 Parallel Readout System 4-th IWORID Amsterdam 8 – 12 September 2002 V. Fanti, R. Marzeddu, P. Randaccio Dipartamento di Fisica e Sezione INFN Cagliari

2. IWORID 2002 - P.Randaccio Dynamic imaging with Medipix2 ONE CHIP 256x256x14 bits per frame 25 frames per second 2.3 x 10 7 bits per second 2.9 x 10 6 bytes per second EIGHT CHIPS 1.8 x 10 8 bits per second 2.3 x 10 7 bytes per second Serial I/O: 180 MHz Parallel I/O 32 bit: 5.7 MHz However, the readout speed should be as high as possible to reduce the dead time; aiming to 10% DT we should reach frequencies 10 times higher.

3. IWORID 2002 - P.Randaccio The PC platform as acquisition system Actually the PC is the best solution for: Acquisition Processing Visualization Storage in imaging systems.

4. IWORID 2002 - P.Randaccio PC architecture North Bridge (Hi speed devices) South Bridge (Low speed devices) I/O & interconnect busses: Host Bus Memory Bus AGP (Graphics) V-link (interbridge connection) ATA (Hard disks) PCI USB IEEE 1394 firewire Legacy (ISA) …. obsolete

5. IWORID 2002 - P.Randaccio Computer speed The typical processor clock frequency is 1 GHz The word length is 32 bits = 4 bytes but …. the data transfer rate is not 4 Gbyte/s ! The speed is limited by the bus clock: Host bus (between CPU and North Bridge): 200 MHz Memory : 200 MHz AGP(4x) : 132 MHz ATA : 100 MHz PCI : 33 MHz ISA : 8 MHz

6. IWORID 2002 - P.Randaccio Maximum transfer speed (the effective one) Parallel busses single modeburst modeDMA Legacy bus 2.7----4.2 PCI bus 1060122 All values expressed in Mbytes/s Serial busses Low speedFull speed USB 1.1 0.21.5 Firewire IEEE1394a 12.550

7. IWORID 2002 - P.Randaccio The PCI bus : essentials Peripheral Component Interconnect (PCI) 32-bit multiplexed data/address bus Clock frequency : 33 MHz (66 MHz) Maximum (theo) transfer rate : 132 MB/s (264 MB/s) 3.3V & 5V operability Plug and Play single mode e burst mode transaction reflected wave switching

8. IWORID 2002 - P.Randaccio Transmission line Standard method: incident wave switching V X V TH bus end Incident wave incident point t < T prop. V X V TH bus end t > T prop. Incident wave VME, ISA, EISA, …. busses BUS R term Slot 1Slot 2Slot 3Slot 4Slot 5Slot 6Slot 7Slot 8Slot 9Slot 10 Incident point

9. IWORID 2002 - P.Randaccio PCI method: reflected wave switching V X V TH bus end Incident wave incident point t < T prop. V X V TH bus end incident point T prop <t <2 T prop. Reflected wave BUS Slot 1Slot 2Slot 3Slot 4Slot 5Slot 6Slot 7Slot 8Slot 9Slot 10 Incident point InitiatorTarget

10. IWORID 2002 - P.Randaccio PCI bus length limit T_cyc Clock device #1 T_low T_hig h T_skew Clock device #2 Dev #nDev #1 d Dev #2 T_prop  10 ns ; d = bus length ; v = 2 ·10 8 m/s Worst case:  x = 2d  x = v ·T_prop = 2 m d  1 m (theo) T prop = 30 ns – T val – T su - T skew

11. IWORID 2002 - P.RandaccioBridge Local bus (CMOS) PCI bus BRIDGE Logic & I/O circuits Connection between PCI bus and local bus for timing, operating voltage (5V/3.3V/2.2V), protocols

12. IWORID 2002 - P.Randaccio PLX PCI9054 Bus Master I/O Accelerator

13. IWORID 2002 - P.Randaccio Bridge PLX9054 Bus Master interface 32-bit data bus, 28-bit address bus 3.3V, 5V tolerant Local bus clock up to 50 MHz Dual DMA channels Six Read/Write FIFOs 16 Lword Single and burst mode operation (block transfer up to 16 LWord) Unlimited burst length Memory spaces remap (up to 256 Mbytes of memory)

14. IWORID 2002 - P.Randaccio Burst read mode Local BusPCI Bus PCI Read Request The bridge prefetches data from Local Bus device at max. clock speed Prefetched data is stored in the internal FIFO PCI bus reads data from the FIFO The PCI bridge returns data from internal FIFO in sequential address read operations until FIFO is empty Read FIFO (16 x 32 bit) Read D 0 Read D 1 Read D 15 = empty= full Read D 2

15. IWORID 2002 - P.Randaccio I/O burst advantage North bridge CPU South Bridge Local Bus PCI Bus FIFO PCI/Local bridge Host/PCI bridge FIFO Host memory Bus access (address, data, control cycles) slows down I/O operation. The prefetch with FIFOs reduces the time needed for bus access operations by a factor 16. CPU reads data directly from FIFO at very high speed.

16. IWORID 2002 - P.Randaccio Reading data from Medipix2 parallel port Acquisition rate is about 64 MByte/s 32 bits - 16 MHz mean acquisition rate PCI bridge reads 16 Lword from Medipix2 parallel port through local bus CPU reads data from FIFO

17. IWORID 2002 - P.Randaccio Most PCs do not support burst read ! If the North Bridge has no FIFO (Intel bridges) the CPU readout phase is slower Acquisition rate is about 10 MByte/s

18. IWORID 2002 - P.Randaccio Reading from a PCI device 1 M 4 G BIOS ROM PCI memory System RAM CPU It is like a memory block transfer from PCI Address Space to program data. From the software point of view it is just a move instruction. Each data transfer between bridges and busses is transparent to the software.

19. IWORID 2002 - P.Randaccio PCI Local Spaces Local bus BRIDGE Space1Space0Space2Space3Space4 Configuration Address Space I/O Address Space A PCI device can be configured as five memory spaces with configurable address offset and range

20. IWORID 2002 - P.Randaccio Memory space reserved for Medipix data Medipix matrix data read through parallel port Serial data Control Status Not assigned Local Space 4 Local Space 3 Local Space 2 Local Space 1 Local Space 0

21. IWORID 2002 - P.Randaccio Medipix2 Testboard 127 I/O & Power Supply PCI BoardMotherboard Flat cables 34-pin MPRS: general schematic

22. IWORID 2002 - P.Randaccio Line drivers from Medipix to DAQ CMOS - LVDS drivers Power Supply, voltage regulator 3.3V – 2.2V Motherboard Drivers Lvds  Cmos Z-adapter Medipix 2.2 V Voltage Regulator Test Board 34-pin I/O flat cables

23. IWORID 2002 - P.Randaccio Motherboard picture Medipix TB ConnectorDRIVERs Voltage Reg. OUT Conn.IN Conn. CMOS  LVDS Z-adapter

24. IWORID 2002 - P.Randaccio DAQ: PCI board PCI Universal card for 32-bit, 33 MHz slot. Main components: PCI Bridge: connection from PCI Bus to Local Bus Registers for output lines Buffers for input lines Address decode circuit Local Clock circuit Voltage regulator 3.3V Serial Eeprom RegistersBuffers Bridge PCI Clock 3.3 V Address Decode EEPROM

25. IWORID 2002 - P.Randaccio PCI Board picture Address decode Input connector Output connector Output registers Input buffers Clock 3.3V reg. EepromBridge

26. IWORID 2002 - P.Randaccio PCI Board picture

27. IWORID 2002 - P.Randaccio Software SoftwareHardware Library Medipix.dll (C++) Control, acquisition & visualization (VBasic) PCI board Motherboard Medipix2

28. IWORID 2002 - P.Randaccio Utility software: PCI board control panel  Scan PCI bus  Open device  Read/write test  Internal registers configuration

29. IWORID 2002 - P.Randaccio Acquisition utilities  Set the DACs  Reset matrix data  Set pixel registers  Readout

30. IWORID 2002 - P.Randaccio Image acquisition timing Medipix2 MPRS Raw data memory MPRS Readout Stop Start X-rays Image reconstruction routine Image Memory Medipix photon counting phase time 2 ms ~38 ms ~ 0 ms

31. IWORID 2002 - P.Randaccio Image reconstruction Any image processing is made by software after the acquisition, in particular: Image reconstruction with deserialization and derandomization The total time is : 256x8x14x32xTs = 917504xTs where Ts is the period of the inner software loop. The reconstruction time depends on CPU speed: however with a normal PC it lasts no more than 10 ms The software does the reconstruction during the Medipix2 photon counting phase, so it does not slow down the process.

32. IWORID 2002 - P.Randaccio Conclusions Parallel readout seems to be appropriate for the Medipix2 dynamic imaging acquisition. Actual PCs are convenient platforms for the image acquisition, processing, storage and visualization. Interfaces based on PCI bus are easy to develop and fast enough for our purposes. The hardware complexity is transparent for the software thanks to the bridges. Image reconstruction made by software simplifies MPRS hardware design.