Review: Designing Inverters for Performance  Reduce C L l internal diffusion capacitance of the gate itself l interconnect capacitance l fanout  Increase.

Review: Designing Inverters for Performance  Reduce C L l internal diffusion capacitance of the gate itself l interconnect capacitance l fanout  Increase W/L ratio of the transistor l the most powerful and effective performance optimization tool in the hands of the designer l watch out for self-loading!  Increase V DD l only minimal improvement in performance at the cost of increased energy dissipation  Slope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values l good for performance l good for power consumption

Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A C int CLCL A RnRn A RpRp B RpRp B RnRn NAND INVERTER B RpRp A RpRp A RnRn B RnRn CLCL NOR

Input Pattern Effects on Delay  Delay is dependent on the pattern of inputs  Low to high transition l both inputs go low -delay is 0.69 R p /2 C L since two p-resistors are on in parallel l one input goes low -delay is 0.69 R p C L  High to low transition l both inputs go high -delay is 0.69 2R n C L  Adding transistors in series (without sizing) slows down the circuit CLCL A RnRn A RpRp B RpRp B RnRn C int

Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time, psec Voltage, V Input Data Pattern Delay (psec) A=B=0  1 69 A=1, B=0  1 62 A= 0  1, B=1 50 A=B=1  0 35 A=1, B=1  0 76 A= 1  0, B=1 57 2-input NAND with NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 10 fF

Transistor Sizing a Complex CMOS Gate OUT = !(D + A (B + C)) D A BC D A B C

Transistor Sizing a Complex CMOS Gate OUT = !(D + A (B + C)) D A BC D A B C 1 2 22 2 2 4 4 6 6 12

Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

t p as a Function of Fan-In t pH L t pL H t p (psec) fan-in quadratic function of fan-in linear function of fan-in  Gates with a fan-in greater than 4 should be avoided. tptp

Fast Complex Gates: Design Technique 1  Transistor sizing l as long as fan-out capacitance dominates  Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output should be the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks

Fast Complex Gates: Design Technique 2  Input re-ordering l when not all inputs arrive at the same time C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path 1 0101 1 1 1 0101 charged

Fast Complex Gates: Design Technique 2  Input re-ordering l when not all inputs arrive at the same time C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 1 1 0101 charged discharged

Sizing and Ordering Effects DCBA D C B A CLCL C3C3 C2C2 C1C1 Progressive sizing in pull-down chain gives up to a 23% improvement. Input ordering saves 5% critical path A – 23% critical path D – 17% 3333 4 4 4 4 4 5 6 7 = 100 fF

Fast Networks: Design Technique 5 - Logical Effort  The optimum fan-out for a chain of N inverters driving a load C L is f =  (C L /C in ) l so, if we can, keep the fan-out per stage around 4.  Can the same approach (logical effort) be used for any combinational circuit? l For a complex gate, we expand the inverter equation t p = t p0 (1 + C ext /  C g ) = t p0 (1 + f/  ) to t p = t p0 (p + g f/  ) -t p0 is the intrinsic delay of an inverter -f is the effective fan-out (C ext /C g ) – also called the electrical effort -p is the ratio of the instrinsic (unloaded) delay of the complex gate and a simple inverter (a function of the gate topology and layout style) -g is the logical effort N

Intrinsic Delay Term, p  The more involved the structure of the complex gate, the higher the intrinsic delay compared to an inverter Gate Typep Inverter1 n-input NANDn n-input NORn n-way mux2n XOR, XNORn 2 n-1 Ignoring second order effects such as internal node capacitances

Logical Effort Term, g  g represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response l the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver it same output current) Gate Typeg (for 1 to 4 input gates) 1234 Inverter1 NAND4/35/3(n+2)/3 NOR5/37/3(2n+1)/3 mux222 XOR412

Example of Logical Effort  Assuming a pmos/nmos ratio of 2, the input capacitance of a minimum-sized inverter is three times the gate capacitance of a minimum-sized nmos (C unit ) A + B A B AB A B A B AB A A A

Example of Logical Effort  Assuming a pmos/nmos ratio of 2, the input capacitance of a minimum-sized inverter is three times the gate capacitance of a minimum-sized nmos (C unit ) A + B A B AB A B A B AB A A A 2 1 C unit = 3 22 2 2 C unit = 4 4 4 11 C unit = 5

Delay as a Function of Fan-Out  The slope of the line is the logical effort of the gate  The y-axis intercept is the intrinsic delay normalized delay fan-out f NAND2: g=4/3, p = 2 INV: g=1, p=1 intrinsic delay effort delay  Can adjust the delay by adjusting the effective fan-out (by sizing) or by choosing a gate with a different logical effort  Gate effort: h = fg

Path Delay of Complex Logic Gate Network  Total path delay through a combinational logic block t p =  t p,j = t p0  (p j + (f j g j )/  )  So, the minimum delay through the path determines that each stage should bear the same gate effort f 1 g 1 = f 2 g 2 =... = f N g N  Consider optimizing the delay through the logic network how do we determine a, b, and c sizes? 1 a b c CLCL 5

Path Delay Equation Derivation  The path logical effort, G =  g i  And the path effective fan-out (path electrical effort) is F = C L /g 1  The branching effort accounts for fan-out to other gates in the network b = (C on-path + C off-path )/C on-path  The path branching effort is then B =  b i  And the total path effort is then H = GFB  So, the minimum delay through the path is D = t p0 (  p j + (N  H)/  ) N

Path Delay of Complex Logic Gates, con’t  For gate i in the chain, its size is determined by s i = (g 1 s 1 )/g i  (f j /b j ) j=1 i-1 1 a b c CLCL 5  For this network l F = C L /C g1 = 5 l G = 1 x 5/3 x 5/3 x 1 = 25/9 l B = 1 (no branching) l H = GFB = 125/9, so the optimal stage effort is  H = 1.93 -Fan-out factors are f 1 =1.93, f 2 =1.93 x 3/5 = 1.16, f 3 = 1.16, f 4 = 1.93 l So the gate sizes are a = f 1 g 1 /g 2 = 1.16, b = f 1 f 2 g 1 /g 3 = 1.34 and c = f 1 f 2 f 3 g 1 /g 4 = 2.60 4

Fast Complex Gates: Design Technique 6  Reducing the voltage swing l linear reduction in delay l also reduces power consumption l requires use of “sense amplifiers” on the receiving end to restore the signal level (will look at their design when covering memory design) t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.69 (3/4 (C L V swing )/ I DSATn )

TG Logic Performance  Effective resistance of the TG is modeled as a parallel connection of R p (= (V DD – V out )/(-I Dp )) and R n (=V DD – V out )/I Dn ) V out, V Resistance, k  RpRp RnRn 2.5V 0V 2.5VV out RpRp RnRn R eq = R n || R p W/L n =0.50/0.25 W/L p =0.50/0.25  So, the assumption that the TG switch has a constant resistive value, R eq, is acceptable

Delay of a TG Chain CCCC VNVN V1V1 ViVi V i+1 5 0 5 0 5 0 5 0 CCCC R eq V in VNVN V1V1 ViVi V i+1 V in  Delay of the RC chain (N TG’s in series) is t p (V n ) = 0.69  kCR eq = 0.69 CR eq (N(N+1))/2  0.35 CR eq N 2 k=1 N

TG Delay Optimization  Can speed it up by inserting buffers every M switches  Delay of buffered chain (M TG’s between buffer) t p = 0.69  N/M CR eq (M(M+1))/2  + (N/M - 1) t pbuf M opt = 1.7  (t pbuf /CR eq )  3 or 4 C V in VNVN 5 0 5 0 5 0 CC 5 0 5 0 C 5 0 C M

Why Power Matters  Packaging costs  Power supply rail design  Chip and system cooling costs  Noise immunity and system reliability  Battery life (in portable systems)  Environmental concerns l Office equipment accounted for 5% of total US commercial energy usage in 1993 l Energy Star compliant systems

Chip Power Density Distribution  Power density is not uniformly distributed across the chip  Silicon is not a good heat conductor  Max junction temperature is determined by hot-spots l Impact on packaging, w.r.t. cooling Power Map On-Die Temperature

Power and Energy Figures of Merit  Power consumption in Watts l determines battery life in hours  Peak power l determines power ground wiring designs l sets packaging limits l impacts signal noise margin and reliability analysis  Energy efficiency in Joules l rate at which power is consumed over time  Energy = power * delay l Joules = Watts * seconds l lower energy number means less power to perform a computation at the same frequency

Power versus Energy Watts time Power is height of curve Watts time Approach 1 Approach 2 Approach 1 Energy is area under curve Lower power design could simply be slower Two approaches require the same energy

PDP and EDP  Power-delay product (PDP) = P av * t p = (C L V DD 2 )/2 l PDP is the average energy consumed per switching event (Watts * sec = Joule) l lower power design could simply be a slower design l allows one to understand tradeoffs better energy-delay energy delay  Energy-delay product (EDP) = PDP * t p = P av * t p 2 l EDP is the average energy consumed multiplied by the computation time required l takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)

Understanding Tradeoffs Energy 1/Delay a b c d Lower EDP  Which design is the “best” (fastest, coolest, both) ? better

CMOS Energy & Power Equations E = C L V DD 2 P 0  1 + t sc V DD I peak P 0  1 + V DD I leakage P = C L V DD 2 f 0  1 + t sc V DD I peak f 0  1 + V DD I leakage Dynamic power Short-circuit power Leakage power f 0  1 = P 0  1 * f clock

Dynamic Power Consumption Energy/transition = C L * V DD 2 * P 0  1 P dyn = Energy/transition * f = C L * V DD 2 * P 0  1 * f P dyn = C EFF * V DD 2 * f where C EFF = P 0  1 C L Not a function of transistor sizes! Data dependent - a function of switching activity! VinVout CLCL Vdd f01f01

Lowering Dynamic Power P dyn = C L V DD 2 P 0  1 f Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations Clock frequency: Increasing… Activity factor: How often, on average, do wires switch?

Short Circuit Power Consumption Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. VinVout CLCL I sc

Short Circuit Currents Determinates  Duration and slope of the input signal, t sc  I peak determined by l the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. l strong function of the ratio between input and output slopes -a function of C L E sc = t sc V DD I peak P 0  1 P sc = t sc V DD I peak f 0  1

Impact of C L on P sc VinVout CLCL I sc  0 VinVout CLCL I sc  I max Large capacitive load Output fall time significantly larger than input rise time. Small capacitive load Output fall time substantially smaller than the input rise time.

I peak as a Function of C L I peak (A) time (sec) x 10 -10 x 10 -4 C L = 20 fF C L = 100 fF C L = 500 fF 500 psec input slope Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. When load capacitance is small, I peak is large.

P sc as a Function of Rise/Fall Times P normalized t sin /t sou t V DD = 3.3 V V DD = 2.5 V V DD = 1.5V normalized wrt zero input rise-time dissipation When load capacitance is small (t sin /t sout > 2 for V DD > 2V) the power is dominated by P sc If V DD < V Tn + |V Tp | then P sc is eliminated since both devices are never on at the same time. W/L p = 1.125  m/0.25  m W/L n = 0.375  m/0.25  m C L = 30 fF

Leakage (Static) Power Consumption Sub-threshold current is the dominant factor. All increase exponentially with temperature! V DD I leakage Vout Drain junction leakage Sub-threshold current Gate leakage

Leakage as a Function of V T 10 -2 10 -12 10 -7  Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation.  An 90mV/decade V T roll-off - so each 255mV increase in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance)

TSMC Processes Leakage and V T 80 0.25 V 13,000 920/400 0.08  m 24 Å 1.2 V CL013 HS 52 0.29 V 1,800 860/370 0.11  m 29 Å 1.5 V CL015 HS 42 Å T ox (effective) 43142230FET Perf. (GHz) 0.40 V0.73 V0.63 V0.42 VV Tn 3000.151.6020I off (leakage) (  A/  m) 780/360320/130500/180600/260I DSat (n/p) (  A/  m) 0.13  m0.18  m0.16  m L gate 2 V1.8 V V dd CL018 HS CL018 ULP CL018 LP CL018 G From MPR, 2000

Exponential Increase in Leakage Currents Temp(C) I leakage (nA/  m) From De,1999

Review: Energy & Power Equations E = C L V DD 2 P 0  1 + t sc V DD I peak P 0  1 + V DD I leakage P = C L V DD 2 f 0  1 + t sc V DD I peak f 0  1 + V DD I leakage Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) Leakage power (~2% today and increasing) f 0  1 = P 0  1 * f clock

Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency EnergyDesign TimeNon-active ModulesRun Time Active Logic Design Reduced V dd Sizing Multi-V dd Clock Gating DFS, DVS (Dynamic Freq, Voltage Scaling) Leakage+ Multi-V T Sleep Transistors Multi-V dd Variable V T + Variable V T

Dynamic Power as a Function of Device Size  Device sizing affects dynamic energy consumption l gain is largest for networks with large overall effective fan-outs (F = C L /C g,1 )  The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s l e.g., for F=20, f opt (energy) = 3.53 while f opt (performance) = 4.47  If energy is a concern avoid oversizing beyond the optimal 1234567 0 0.5 1 1.5 f normalized energy F=1 F=2 F=5 F=10 F=20 From Nikolic, UCB

Dynamic Power Consumption is Data Dependent ABOut 001 010 100 110 2-input NOR Gate With input signal probabilities P A=1 = 1/2 P B=1 = 1/2 Static transition probability P 0  1 = P out=0 x P out=1 = P 0 x (1-P 0 )  Switching activity, P 0  1, has two components l A static component – function of the logic topology l A dynamic component – function of the timing behavior (glitching) NOR static transition probability = 3/4 x 1/4 = 3/16

NOR Gate Transition Probabilities CLCL A B BA P 0  1 = P 0 x P 1 = (1-(1-P A )(1-P B )) (1-P A )(1-P B ) PAPA PBPB 0 101  Switching activity is a strong function of the input signal statistics l P A and P B are the probabilities that inputs A and B are one

Transition Probabilities for Some Basic Gates P 0  1 = P out=0 x P out=1 NOR(1 - (1 - P A )(1 - P B )) x (1 - P A )(1 - P B ) OR(1 - P A )(1 - P B ) x (1 - (1 - P A )(1 - P B )) NANDP A P B x (1 - P A P B ) AND(1 - P A P B ) x P A P B XOR(1 - (P A + P B - 2P A P B )) x (P A + P B - 2P A P B ) B A Z X 0.5 For Z: P 0  1 = For X: P 0  1 =

Transition Probabilities for Some Basic Gates P 0  1 = P out=0 x P out=1 NOR(1 - (1 - P A )(1 - P B )) x (1 - P A )(1 - P B ) OR(1 - P A )(1 - P B ) x (1 - (1 - P A )(1 - P B )) NANDP A P B x (1 - P A P B ) AND(1 - P A P B ) x P A P B XOR(1 - (P A + P B - 2P A P B )) x (P A + P B - 2P A P B ) B A Z X 0.5 For Z: P 0  1 = P 0 x P 1 = (1-P X P B ) P X P B For X: P 0  1 = P 0 x P 1 = (1-P A ) P A = 0.5 x 0.5 = 0.25 = (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16

Inter-signal Correlations  Determining switching activity is complicated by the fact that signals exhibit correlation in space and time l reconvergent fan-out B A Z X P(Z=1) = P(B=1) & P(A=1 | B=1) Reconvergent fan-out 0.5  Have to use conditional probabilities

Inter-signal Correlations B A Z X P(Z=1) = P(B=1) & P(A=1 | B=1) 0.5 (1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16 (1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085 Reconvergent  Determining switching activity is complicated by the fact that signals exhibit correlation in space and time l reconvergent fan-out  Have to use conditional probabilities

Logic Restructuring Chain implementation has a lower overall switching activity than the tree implementation for random inputs Ignores glitching effects  Logic restructuring: changing the topology of a logic network to reduce transitions A B C D F A B C DZ F W X Y 0.5 (1-0.25)*0.25 = 3/16 0.5 7/64 15/256 3/16 15/256 AND: P 0  1 = P 0 x P 1 = (1 - P A P B ) x P A P B

Input Ordering A B C X F 0.5 0.2 0.1 B C A X F 0.2 0.1 0.5 Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5)

Input Ordering Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5) A B C X F 0.5 0.2 0.1 B C A X F 0.2 0.1 0.5 (1-0.5x0.2)x(0.5x0.2)=0.09(1-0.2x0.1)x(0.2x0.1)=0.0196

Glitching in Static CMOS Networks ABC X Z 101000 Unit Delay A B X Z C  Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) l glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value

Glitching in an RCA S0 S1 S2S14 S15 Cin S0 S1 S2 S3 S4 S5 S10 S15

Balanced Delay Paths to Reduce Glitching So equalize the lengths of timing paths through logic F1F1 F2F2 F3F3 0 0 0 0 1 2 F1F1 F2F2 F3F3 0 0 0 0 1 1  Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs

Dynamic Power as a Function of V DD  Decreasing the V DD decreases dynamic energy consumption (quadratically)  But, increases gate delay (decreases performance) V DD (V) t p(normalized)  Determine the critical path(s) at design time and use high V DD for the transistors on those paths for speed. Use a lower V DD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits).

Multiple V DD Considerations  How many V DD ? – Two is becoming common l Many chips already have two supplies (one for core and one for I/O)  When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (step-up) l If a gate supplied with V DDL drives a gate at V DDH, the PMOS never turns off -The cross-coupled PMOS transistors do the level conversion -The NMOS transistor operate on a reduced supply l Level converters are not needed for a step-down change in voltage l Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flipflop (see Figure 11.47) V DDH V in V out V DDL

Dual-Supply Inside a Logic Block  Minimum energy consumption is achieved if all logic paths are critical (have the same delay)  Clustered voltage-scaling l Each path starts with V DDH and switches to V DDL (gray logic gates) when delay slack is available l Level conversion is done in the flipflops at the end of the paths

Stack Effect  Leakage is a function of the circuit topology and the value of the inputs V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) where V T0 is the threshold voltage at V SB = 0; V SB is the source- bulk (substrate) voltage;  is the body-effect coefficient AB B A Out VXVX ABVXVX I SUB 00V T ln(1+n)V GS =V BS = -V X 010V GS =V BS =0 10V DD -V T V GS =V BS =0 110V SG =V SB =0  Leakage is least when A = B = 0  Leakage reduction due to stacked transistors is called the stack effect

Short Channel Factors and Stack Effect  In short-channel devices, the subthreshold leakage current depends on V GS,V BS and V DS. The V T of a short-channel device decreases with increasing V DS due to DIBL (drain-induced barrier loading). l Typical values for DIBL are 20 to 150mV change in V T per voltage change in V DS so the stack effect is even more significant for short-channel devices. l V X reduces the drain-source voltage of the top nfet, increasing its V T and lowering its leakage  For our 0.25 micron technology, V X settles to ~100mV in steady state so V BS = -100mV and V DS = V DD -100mV which is 20 times smaller than the leakage of a device with V BS = 0mV and V DS = V DD

Leakage as a Function of Design Time V T  Reducing the V T increases the subthreshold leakage current (exponentially) l 90mV reduction in V T increases leakage by an order of magnitude  But, reducing V T decreases gate delay (increases performance)  Determine the critical path(s) at design time and use low V T devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control. l A careful assignment of V T ’s can reduce the leakage by as much as 80%

Dual-Thresholds Inside a Logic Block  Minimum energy consumption is achieved if all logic paths are critical (have the same delay)  Use lower threshold on timing-critical paths l Assignment can be done on a per gate or transistor basis; no clustering of the logic is needed l No level converters are needed

Variable V T (ABB) at Run Time  V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) V SB (V) V T (V)  A negative bias on V SB causes V T to increase  Adjusting the substrate bias at run time is called adaptive body-biasing (ABB) l Requires a dual well fab process  For an n-channel device, the substrate is normally tied to ground (V SB = 0)

Review: Designing Inverters for Performance  Reduce C L l internal diffusion capacitance of the gate itself l interconnect capacitance l fanout  Increase.

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Review: Designing Inverters for Performance  Reduce C L l internal diffusion capacitance of the gate itself l interconnect capacitance l fanout  Increase.

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Presentation on theme: "Review: Designing Inverters for Performance  Reduce C L l internal diffusion capacitance of the gate itself l interconnect capacitance l fanout  Increase."— Presentation transcript:

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