1. ECE 545 Digital System Design with VHDL
Fall 2015

2. Research and teaching interests:
Kris Gaj
Research and teaching interests:
reconfigurable computing
computer arithmetic
cryptography
network security
Contact:
The Engineering Building, room 3225
Office hours: Thursday, 6:00-7:00 PM, Tuesday, 6:00-7:00 PM,
and by appointment

3. Digital System Design with VHDL
Course Web Page
ECE web page  Courses 
Digital System Design with VHDL
(or Google “Kris Gaj”)

4. MS in Computer Engineering
ECE 545
Part of:
MS in Computer Engineering
One of five core courses
(must be passed with B or better)
Fundamental course for the specialization areas:
Digital Systems Design
Digital Signal Processing
Elective course in the remaining specialization areas
MS in Electrical Engineering
Elective

5. PhD in Electrical and Computer Engineering
ECE 545
Part of:
PhD in Electrical and Computer Engineering
Knowledge tested at the
Technical Qualifying Exam (TQE)
Topic 2: Digital Design and Computer Organization

6. Recommended program & specialization I am interested in…
I want to specialize
primarily in…
CAD tools & Design Automation
Hardware Description Languages
FPGAs & Reconfigurable computing
Computer Arithmetic
Front-end ASIC Design (algorithmic downto gate level)
Back-end ASIC Design (circuit and mask layout levels)
Analog & Digital Circuit Design
VLSI Fabrication
Microelectronics
Nanoelectronics
Semiconductor Devices
MS CpE
Digital Systems Design
VLSI
Digital Systems Design
ASICs & FPGAs
VHDL/Verilog
CAD Tools
Reconfigurable
Computing
Microelectronics
VLSI Fabrication
Nanoelectronics
MS EE
Microelectronics/
Nanoelectronics

7. Courses Design level Digital System Design with VHDL Computer
Arithmetic
VLSI Design
for ASICs
VLSI Test
Concepts
algorithmic
ECE
545
ECE
699
ECE
645
SW/HW
Codesign
register-transfer
ECE
681
ECE
682
gate
ECE
586
transistor
Digital
Integrated
Circuits
ECE
680
layout
Physical VLSI Design
Semiconductor
Device Fundamentals
MOS Device
Electronics
ECE 584
ECE684
devices

8. CpE CpE Microprocessors and Digital Systems Design Embedded Systems
ECE 545 Digital System Design
with VHDL
ECE 586 Digital Integrated Circuits
ECE 645 Computer Arithmetic
ECE 681 VLSI Design for ASICs
ECE 682 VLSI Test Concepts ECE 699 SW/HW Codesign
ECE 740 DSP HW Architectures
ECE 510 Real-Time Concepts
ECE 511 Microprocessors
ECE 611 Advanced Microprocessors
ECE 612 Real-Time Emb. Systems
ECE 641 Computer System Arch.
ECE 699 SW/HW Codesign
ECE 699 Green Computing and
Heterogeneous Architectures
Pre-
Approved
Electives
ECE 545, 645, 681 (digital design)
CS 571 (operating systems)
CS 540, 583 (languages, algorithms)
CS 580 (artificial intelligence)
ECE 542, 642, 742 (networks)
ECE 548 (sequential mach. theory)
ECE 584, 684, … (technology)
ECE 511, 611, … (microprocessors)
ECE 535, 537, 646, …(applications:
DSP, image processing, crypto, etc.)
Suggested
Electives
K. Gaj, H. Homayoun, J-P. Kaps
T. Storey, A. Cohen
H. Homayoun, J. Kaps, P. Pachowicz, C. Sabzevari
Professors

9. DIGITAL SYSTEMS DESIGN
ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL
ECE 699 Software/Hardware Codesign
– K. Gaj, homework, SoC design with VHDL and C
3. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL or Verilog
4. ECE 681 VLSI Design for ASICs – H. Homayoun, project/lab, front-end and back-end ASIC design with Synopsys tools
5. ECE 586 Digital Integrated Circuits – D. Ioannou, R. Mulpuri, homework
6a. ECE 682 VLSI Test Concepts
– T. Storey, homework
6b. ECE 740 Digital Signals Processing Hardware Architectures – A. Cohen, project, FPGA design with VHDL and Matlab/Simulink

10. MICROPROCESSOR AND EMBEDDED SYSTEMS
ECE 510 Real-Time Concepts – P. Pachowicz, project, design of real-time systems
2. ECE 511 Microprocessors
– J.P. Kaps, project, system based on MSP430 microcontroller
3. ECE 611 Advanced Microprocessors
– H. Homayoun, project, computer architecture simulation tools
4. ECE 612 Real-Time Embedded System
– C. Sabzevari, project, programming distributed real-time systems
5. ECE 641 Computer System Architecture
ECE 699 Software/Hardware Codesign
– K. Gaj, homework, SoC design with VHDL and C
7. ECE 699 Heterogeneous Architectures and Green Computing

11. in the Cryptographic EngineeringTA
Sanjay Deshpande
help with the installation
and configuration of CAD tools
help with understanding of tutorials
and the operation of tools
help with VHDL and tool-oriented
homework assignments
limited help with debugging your
project codes
MS Thesis Student
in the Cryptographic Engineering
Research Group (CERG)

12. Getting Help Outside of Office Hours
System for asking questions 24/7
Answers can be given by students and instructors
Student answers endorsed (or corrected) by instructors
Average response time in Fall 2014 = 1.5 hour
You can submit your questions anonymously
You can ask private questions visible only to
the instructors

13. Grading Scheme Project - 35% Midterm Exam - 20% Final Exam - 30%
Homework %
Project %
Midterm Exam %
Final Exam %
Class Activity Bonus 5%

14. Bonus Points for Class Activity
Based on class exercises during lecture
“Small” points earned each week posted on BlackBoard
Up to 5 “big” bonus points
Scaled based on the performance of the best student
For example:
Small points
Big points
1. Alice
Bob
… … …
28. Charlie

15. Midterm exam 1 2 hours 40 minutes in class design-oriented
open-books, cheat sheet
practice exams available on the web
Tentative date:
Last week of October

16. Final exam 2 hours 45 minutes in class design-oriented
open-books, cheat sheet
practice exams available on the web
Date:
Thursday, December 17, 7:30-10:15pm

17. Textbooks

18. Required Textbook Pong P. Chu, RTL Hardware Design Using VHDL,
Wiley-Interscience, 2006.

19. Supplementary Textbook – Basics Refresher
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3rd or 2nd Edition

20. Supplementary Textbook – Advanced
Hubert Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press; 1st Edition, 2008.

21. Technology
&
Tools

22. What is an FPGA? Configurable Logic Blocks (CLB) / Adaptive Logic
Modules (ALM)
Block RAMs
I/O
Blocks
Block
RAMs

23. Modern FPGA (#Logic resources, #Multipliers/DSP units, #RAM_blocks)
(CLBs or ALMs)
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

24. General structure of an FPGA
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (
ECE 448 – FPGA and ASIC Design with VHDL

25. 4-input LUT (Look-Up Table) (used in earlier families of FPGAs)
Look-Up tables are primary elements for logic implementation
Each LUT can implement any function of 4 inputs

26. 6-Input LUT of Spartan-6 ECE 448 – FPGA and ASIC Design with VHDL
When the CLB LUT is configured as memory, it can implement 16x1 synchronous RAM. One LUT can implement 16x1 Single-Port RAM. Two LUTs are used to implement 16x1 dual port RAM. The LUTs can be cascaded for desired memory depth and width.
The write operation is synchronous. The read operation is asynchronous and can be made synchronous by using the accompanying flip flops of the CLB LUT.
The distributed ram is compact and fast which makes it ideal for small ram based functions.
ECE 448 – FPGA and ASIC Design with VHDL

27. Two competing implementation
approaches
FPGA
Field Programmable
Gate Array
ASIC
Application Specific
Integrated Circuit
designed all the way
from behavioral description
to physical layout
no physical layout design;
design ends with
a bitstream used
to configure a device
designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
bought off the shelf
and reconfigured by
designers themselves

28. FPGAs vs. ASICs FPGAs ASICs Off-the-shelf High performance
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes)
Reconfigurability

29. Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp.
Lattice Semiconductor
Atmel
Achronix
Flash & antifuse FPGAs
Microsemi SoC Products Group (formerly Actel Corp.)
Quick Logic Corp.
~ 51% of the market
~ 85%
~ 34% of the market

30. Xilinx FPGA Families Technology Low-cost High-performance 220 nm
Virtex
180 nm
Spartan-II, Spartan-IIE
120/150 nm
Virtex-II, Virtex-II Pro
90 nm
Spartan-3
Virtex-4
65 nm
Virtex-5
45 nm
Spartan-6
40 nm
Virtex-6
28 nm
Artix-7
Virtex-7
20 nm
Virtex UltraSCALE
16 nm
Virtex UltraSCALE+

31. Altera FPGA Devices Technology Low-cost Mid-range High-performance
130 nm
Cyclone
Stratix
90 nm
Cyclone II
Stratix II
65 nm
Cyclone III
Arria I
Stratix III
40 nm
Cyclone IV
Arria II
Stratix IV
28 nm
Cyclone V
Arria V
Stratix V
20 / 14 nm
Arria 10
Stratix 10

32. FPGA Family

33. Spartan-6 FPGA Family

34. FPGA Design process (1) Specification / Pseudocode
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
Specification / Pseudocode
On-paper hardware design
(Block diagram & ASM chart)
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic; );
end AES_core;
Functional simulation
Synthesis
Post-synthesis simulation

35. FPGA Design process (2) Implementation Timing simulation Results
Configuration
On chip testing

36. Levels of design description
Levels supported by HDL
Algorithmic level
Level of description
most suitable for synthesis
Register Transfer Level
Logic (gate) level
Circuit (transistor) level
Physical (layout) level

37. Register Transfer Level (RTL) Design Description
Combinational
Logic
Registers

38. Synthesis

39. Logic Synthesis VHDL description Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;

40. Circuit netlist (RTL view)

41. Implementation

42. Mapping
LUT0
FF1
LUT1
FF2
LUT2

43. Placing
FPGA
CLB SLICES

44. Routing
FPGA
Programmable Connections

45. Configuration
Once a design is implemented, you must create a file that the FPGA can understand
This file is called a bitstream: a BIT file (.bit extension)
The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

46. Simulation Tools

49. FPGA Synthesis Tools
XST

50. Logic Synthesis VHDL description Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;

51. FPGA Implementation
After synthesis the entire implementation process is performed by FPGA vendor tools

52. Design Process control from Active-HDL

53. Xilinx FPGA Tools ECE Labs Aldec Active-HDL Design Flow Xilinx ISE
Aldec Active-HDL (IDE)
ISim or ModelSim
Xilinx XST or
Synopsys Synplify Premier
Xilinx ISE Design Suite
Xilinx XST or
Synopsys Synplify Premier
Xilinx ISE Design Suite (IDE)
simulation
synthesis
implementation

54. Xilinx FPGA Tools Home Aldec Active-HDL Xilinx ISE Design Flow
ISim
Aldec Active-HDL
Student Edition (IDE)
Xilinx XST (restricted)
Xilinx XST (restricted)
Xilinx ISE WebPACK
(restricted)
Xilinx ISE WebPACK (IDE)
(restricted)
simulation
synthesis
implementation

55. Altera FPGA Tools ECE Labs Altera Design Flow
Mentor Graphics ModelSim-Altera
Altera Quartus II Subscription Edition
simulation
synthesis & implementation

56. Altera FPGA Tools Home Altera Design Flow
Mentor Graphics ModelSim-Altera Starter
(restricted)
Altera Quartus II Web Edition
(restricted)
simulation
synthesis & implementation

57. Lab Access Rules and Behavior Code
Please refer to
ECE Labs website
and in particular to
Access rules & behavior code

58. ATHENa – Automated Tool for Hardware EvaluatioN
Supported in part by the National Institute of Standards & Technology (NIST)

59. GMU ATHENa Team Venkata “Vinny” MS CpE student Ekawat
“Ice” PhD CpE student
Marcin
PhD ECE student
John
MS CpE student
Rajesh
PhD ECE student
Michal
PhD exchange
student from
Slovakia

60. ATHENa – Automated Tool for Hardware EvaluatioN
Benchmarking open-source tool,
written in Perl, aimed at an AUTOMATED generation of
OPTIMIZED results for
MULTIPLE hardware platforms
Currently under development at
George Mason University.

61. Why Athena? "The Greek goddess Athena was frequently
called upon to settle disputes between
the gods or various mortals. 
Athena Goddess of Wisdom was
known for her superb logic and intellect.
Her decisions were usually well-considered,
highly ethical, and seldom motivated
by self-interest.”
from "Athena, Greek Goddess
of Wisdom and Craftsmanship"

62. Basic Dataflow of ATHENa
User
FPGA Synthesis and Implementation 6 5
Ranking
of designs 2 3
Database
query
HDL + scripts +
configuration files
Result Summary
+ Database Entries
ATHENa
Server 1
HDL + FPGA Tools
Download scripts and configuration files8 4
Database Entries
Designer
Interfaces + Testbenches 62

63. synthesizable source files
constraint files
configuration files
testbench
synthesizable source files
database entries
(machine- friendly)
result summary
(user-friendly)

64. ATHENa Major Features (1)
synthesis, implementation, and timing analysis in batch mode
support for devices and tools of multiple FPGA vendors:
generation of results for multiple families of FPGAs of a given vendor
automated choice of a best-matching device within a given family

65. ATHENa Major Features (2)
automated verification of designs through simulation in batch mode
support for multi-core processing
automated extraction and tabulation of results
several optimization strategies aimed at finding
optimum options of tools
best target clock frequency
best starting point of placement OR

66. Generation of Results Facilitated by ATHENa
batch mode of FPGA tools
ease of extraction and tabulation of results
Text Reports, Excel, CSV (Comma-Separated Values)
optimized choice of tool options
GMU_optimization_1 strategy
vs.

67. Relative Improvement of Results from Using ATHENa Virtex 5, 256-bit Variants of Hash Functions
Ratios of results obtained using ATHENa suggested options
vs. default options of FPGA tools

68. Other (Somewhat) Similar Tools
Vivado
Design Space Explorer (DSE)
Boldport Flow
EDAx10 Cloud Platform

69. Distinguishing Features of ATHENa
Support for multiple tools from multiple vendors
Optimization strategies aimed at the best possible
performance rather than design closure
Extraction and presentation of results
Seamless integration with the ATHENa database of results

70. Benchmarking Goals Facilitated by ATHENa
Comparing multiple:
cryptographic algorithms
hardware architectures or implementations of the same cryptographic algorithm
hardware platforms from the point of view of their suitability for the implementation of a given algorithm, (e.g., choice of an FPGA device or FPGA board)
tools and languages in terms of quality of results they generate (e.g. Verilog vs. VHDL, Synplicity Synplify Premier vs. Xilinx XST, ISE v vs. ISE v. 14.6)

71. Project

72. Cryptography Project related to the research project conducted by
Cryptographic Engineering Research Group (CERG)
at GMU
supporting NIST (National Institute of Standards
and Technology) and the CAESAR Contest Committee in the evaluation of candidates
for a new cryptographic standard

73. Cryptography Project
RTL VHDL implementation of an authenticated cipher
based on the
algorithm specification
reference implementation in C
Hardware API specification.
a different cipher for each student
two students working on the similar ciphers
can work closely together, and exchange the source
codes
each student graded based on the deliverables
for his/her own cipher

74. Combining Projects from Two Different Courses
ECE 545 & ECE 646
ECE 545 project can be extended into an ECE 646 hardware
project by adding additional ciphers, architectures,
modes of operation, etc.
ECE 646 students must write a final report and submit
deliverables (one submission per group)
ECE 545 submit only deliverables (separate for each member of
a group)
Students forming a two-member group in ECE 646 will receive
the same score for the ECE 646 project, but possibly different
scores for their respective ECE 545 projects
ECE 545 & ECE 797/798/799/998
ECE 545 project can be extended into a Scholarly Paper,
Research Project, Master’s Thesis, PhD Thesis

75. Project Organization Project divided into phases
Deliverables for each phase submitted using Blackboard at selected checkpoints and evaluated by the instructor and/or TA
Feedback provided to the students on the best effort basis
Periodical individual/group meetings devoted to the discussion of each phase deliverables and encountered difficulties
Final deliverables submitted using Blackboard at the end of the semester
Final project score based only on the final deliverables

76. Honor Code Rules
All students are expected to write and debug their project codes individually or in groups of two
All homework assignments should be done individually
Students are encouraged to help and support each other in all problems related to the - operation of the CAD tools - understanding of an investigated algorithm and existing implementations - understanding of the project tasks

77. ECE 545 Questionnaire