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Improving Compression Ratio, Area Overhead, and Test Application Time in System-on-a-chip Test Data Compression/Decompression Paul Theo Gonciari*, Bashir.

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Presentation on theme: "Improving Compression Ratio, Area Overhead, and Test Application Time in System-on-a-chip Test Data Compression/Decompression Paul Theo Gonciari*, Bashir."— Presentation transcript:

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2 Improving Compression Ratio, Area Overhead, and Test Application Time in System-on-a-chip Test Data Compression/Decompression Paul Theo Gonciari*, Bashir Al-Hashimi* and Nicola Nicolici** *University of Southampton, UK **McMaster University, Canada

3 2 Paul Theo Gonciari University of Southampton, UK Why Test Data Reduction ? Exponential increase in volume of test data (ITRS) 60% of ATE upgrade caused by memory (EETimes) Solutions Built-in self-test (BIST) Test data reduction Useful Useless Useful Compaction –does not reduce bandwidth Compression –reduces bandwidth –further reduces test time

4 3 Paul Theo Gonciari University of Southampton, UK Overview Test data compression (TDC) Environment Previous work Variable-length Input Huffman Coding (VIHC) Compression algorithm Decompression architecture Experimental results Conclusions & Future work

5 4 Paul Theo Gonciari University of Southampton, UK Test Data Compression (TDC) Post ATPG process Reduces size of test set Exploits nature of test sets: Mapping Reordering Difference sequence Exploits nature of patterns: Length Type Requires on-chip decoder Test vector database ATPG Test data compression Compressed test set Initial test set

6 5 Paul Theo Gonciari University of Southampton, UK TDC Environment (TDCE) Compression ratio Mapping & reordering Type of input patterns Length of the pattern Compression algorithm Area overhead Nature of decoder Type of input pattern Length of pattern Test application time (TAT) Nature of decoder Length of pattern Frequency ratio on-chip decoder ATE CUT reduced bandwidth Initial test set

7 6 Paul Theo Gonciari University of Southampton, UK TDC – Previous Work Selective Coding (SC) [Jas et. al – VTS99] large decoder parallel decoder low TAT Golomb codes [Chandra et. al – TCAD01] small decoder serial decoder large TAT FDR codes [Chandra et. al – VTS01] fixed size decoder serial decoder large TAT

8 7 Paul Theo Gonciari University of Southampton, UK Variable-length Input Huffman Coding Variable-length Input Huffman Coding (VIHC) Employs variable-length input patterns Uses Huffman coding to obtain optimum code Uses parallel on-chip decoder to reduce TAT Compression Algorithm Step 1 - Prepare initial test set –mapping dont cares –reordering number of 1s in the difference is minimum minimum run of 0s maximum Step 2 - Huffman code computation –exploits variable length patterns Step 3 - Generate decoder information –determines the on-chip decoder

9 8 Paul Theo Gonciari University of Southampton, UK VIHC - Code Computation h = 26 bits t init m = 4 t init 1010000 00010000001 = 16 bits t cmp t 1011100100011010 0000 0 0 0 1 1 0 1 1 1 0001 001 01 Huffman tree Occurrence L 0 1 =1 L 1 1 = 01 L 2 1 = 001 L 3 1 = 0001 L 4 00004 = Pattern Dictionary 000 001 010 011 1 Code

10 9 Paul Theo Gonciari University of Southampton, UK VIHC vs. Golomb [TCAD01] = 26 bits t init = 17 bits t cmp V t G = 19 bits h m = 4 t init 1010000 000100001 01 cmp t V 101010111100 011 cmp t G 1011100100011 001 1 1 1 011 001 01 1 000 1 000 0000 1 Golomb codeRun of 0s 0000 0000 0000 0001 L 4 0000 L 3 L 1 L 0 1 010 011 00 CodePattern Occ. = 4 = 00011 = 012 =1 2

11 10 Paul Theo Gonciari University of Southampton, UK VIHC – Decoder VIHC parallel on-chip decoder Huffman decoder Control and Generation Unit (CGU) scan clock data out ATE sync FSM clock data in CGU special chip test clock FSM clk Huffman decoder datacode

12 11 Paul Theo Gonciari University of Southampton, UK Compression Ratio Comparison

13 12 Paul Theo Gonciari University of Southampton, UK Area Overhead Comparison

14 13 Paul Theo Gonciari University of Southampton, UK Test Application Time Comparison

15 14 Paul Theo Gonciari University of Southampton, UK Comparison Overview similar improved

16 15 Paul Theo Gonciari University of Southampton, UK Conclusion & Future Work Proposed New VIHC method New compression/decompression scheme Improves all the TDCE parameters Good compression ratio Small area overhead Low test application time Future work Reduce synchronization overhead Exploit core wrapper design for TDC


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