1. ECE 448 FPGA and ASIC Design with VHDL Spring 2010

2. ECE 448 Team Course Instructor: Kris Gaj kgaj@gmu.edu Lab Instructors (TAs): Monday & Tuesday section: Jeremy Kelly jeremy.a.kelly (at) gmail.com Wednesday section: John Pham jhnphm (at) gmail.com Thursday section: Brian Loop bdloop (at) gmail.com

3. ECE 448 Team – Division of Tasks Course Instructor – Primary Responsibilities - Lectures - Preparing and grading exams and quizzes - Coordination of work on development of new experiments - Instructions for the lab experiments - Coordination of work done by the TAs - Enforcing consistent policies and grading standards - Mid-semester student satisfaction survey - Resolving conflicts and providing feedback to the TAs - Holding office hours

4. ECE 448 Team – Division of Tasks Lab Instructors (TAs) – Primary Responsibilities - Teaching hands-on sessions on how to use software, hardware and testing equipment needed for experiments - Introductions to the lab experiments - Grading student demonstrations and reports - Holding office hours - Development and testing of new lab experiments

5. You are welcome to attend any of the multiple office hour sessions Please attend the class meetings of the other section only in case of emergency and give preference in access to the lab computers to the students attending their own section All experiment demonstrations need to be done in the presence of your TA, and can be done exclusively during the class time of your section ECE 448 Section Assignment Rules

6. Course Hours Lecture: Monday, Wednesday 5:55-7:10 PM, Lecture Hall, room 2 Lab Sessions: Monday, Tuesday, Wednesday, Thursday 7:20-10:00 PM, The Nguyen Engineering Bldg., room 3208 There will be no lab meetings in the first week of classes!!!

7. Tentative Office Hours Saturday, 12:00-1:00 PM, John Pham, Engineering 3208 Monday, 7:30-8:30 PM, Kris Gaj, Engineering 3225 Monday, 10:00-11:00 PM, Jeremy Kelly, Engineering 3208 Tuesday, 6:00-7:10 PM, Jeremy Kelly, Engineering 3208 Wednesday, 4:30-5:30 PM, Kris Gaj, Engineering 3225 Wednesday, 7:30-8:30 PM, Brian Loop, Engineering 3204

8. Lab Access Rules and Behavior Code Please refer to Computer Engineering Lab website and in particular to Access rules & behavior code

9. Grading criteria First part of the semester (before the Spring break) Second part of the semester (after the Spring break) Lab experiments - Part I 20% Final exam 25% Lab experiments - Part II 20% Midterm exam for the lecture: 10% Midterm exam for the lab: 15% Quizzes & homework: 5%

10. Required Textbook Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience, 2008. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, 3 rd or 2 nd Edition Recommended Textbook current ECE 331/332 book

11. ECE 331 ECE 332 ECE 445  C ECE 447  C ECE 448 Undergraduate Computer Engineering Courses ECE 492 ECE 493 CS 222 BS EE BS CpE Color code:  C CS 262 CS 211 CS 112 CS 367  C

14. VHDL: - writing synthesizable RTL level code in VHDL - writing test benches FPGAs: - architecture of FPGA devices - tools for the computer-aided design with FPGAs - current FPGA families & future trends Topics ECE 448, FPGA and ASIC Design with VHDL

15. Applications: - basics of computer arithmetic - applications from communications, cryptography, digital signal processing, bioengineering, etc. - FPGA boards - microprocessor board–FPGA board interfaces - reconfigurable computers High-level ASIC Design: - standard cell implementation approach - logic synthesis tools - differences between FPGA & standard-cell ASIC design flow New trends: - using high-level programming languages to design hardware - microprocessors embedded in FPGAs Platforms:

16. Tasks of the course Advanced course on digital system design with VHDL Comprehensive introduction to FPGA & front-end ASIC technology Testing equipment - writing VHDL code for synthesis - design using finite state machines and algorithmic state machines - testbenches - hardware: Xilinx FPGAs, Library of standard ASIC cells - software: VHDL simulators Synthesis tools Xilinx ISE - oscilloscopes - logic analyzer

17. VHDL for Specification VHDL for Simulation VHDL for Synthesis

18. Levels of design description Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level Level of description most suitable for synthesis

19. Register Transfer Level (RTL) Design Description Combinational Logic Combinational Logic Registers …

20. VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers, counters, etc. State machines Sequential statements Subset most suitable for synthesis Testbenches

21. Testbench Environment TB Processes Generating Stimuli Design Under Test (DUT) Stimuli All DUT Inputs Simulated Outputs

22. World of Integrated Circuits Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLDFPGA PALPLAPML LUT (Look-Up Table) MUXGates

23. Block RAMs Configurable Logic Blocks I/O Blocks What is an FPGA? Block RAMs

24. designs must be sent for expensive and time consuming fabrication in semiconductor foundry bought off the shelf and reconfigured by designers themselves Two competing implementation approaches ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array designed all the way from behavioral description to physical layout no physical layout design; design ends with a bitstream used to configure a device

25. FPGAs vs. ASICs ASICs FPGAs High performance Off-the-shelf Short time to the market Low development costs Reconfigurability Low power Low cost (but only in high volumes)

26. FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis On-paper hardware design (Block diagram & ASM chart)

27. FPGA Design process (2) Implementation Configuration Timing simulation On chip testing

28. Simulation Tools

31. FPGA Synthesis Tools

32. architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

33. FPGA Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

35. Design Process control from Active-HDL

36. Top Level ASIC Digital Design Flow RTL Design Place+Route Physical Verification Synthesis Design Inception Design Complete Macro Development

37. ASIC Simulation Tools

38. ASIC Synthesis Tools

39. Xilinx FPGA Tools Aldec Active HDL ModelSim Xilinx Edition Synopsys Synplify Pro Xilinx XST Xilinx ISE Xilinx XST (limited) Xilinx WebPACK (limited) ECE LabsHome Aldec Active HDL Student Edition Xilinx XST (limited) Xilinx WebPACK (limited) Windows

40. Digilent Basys2 FPGA Board

42. FPGA available on the board Xilinx Spartan 3E-100, XC3S100E FPGA 100,000 equivalent logic gates 960 CLB slices Programmable Interconnects Configurable Logic Block slices (CLB slices) Block RAMs 72 kbits of memory in block RAMs

44. Digital system design technologies coverage in the CpE & EE programs at GMU Microprocessors ASICs FPGAs ECE 445 ECE 447 ECE 586 ECE 681 ECE 448 ECE 511 ECE 611 ECE 431 Computer Organization Single Chip Microcomputers FPGA and ASIC Design with VHDL Digital Circuit Design Microprocessors Advanced Microprocessors Digital Integrated Circuits VLSI Design for ASICs ECE 545 Digital System Design with VHDL ECE 645 Computer Arithmetic

45. Why ECE 448 is a challenging course? need to “relearn” VHDL need to learn new tools need to perform practical experiments time needed to complete experiments

46. ECE 448: Spring 2006 Student Survey Summary

47. Difficulties finding time to do the labs - 15 learning VHDL – 2 getting used to software – 1

48. 0 1 2 3 4 5 6 7 8 9 26810152024303248 Average time spent per one experiment

49. Self-evaluation 8 – worse than expected 16 – as well as expected 3 – better than expected

50. Why is this course worth taking? VHDL for synthesis: one of the most sought-after skills knowledge of state-of-the-art tools used in the industry knowledge of the modern FPGA & ASIC technologies knowledge of state-of-the-art testing equipment design portfolio that can be used during job interviews unique knowledge and practical skills that make you competitive on the job market