1. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Normalized Comparison of Architectures April 11, 2007 W. Rhett Davis NC State University

2. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 2 Today’s Lecture l Introduction Scaling down to 1.0  m Scaling from 1.0  m down to 0.35  m Scaling from 0.6  m to 0.35  m Scaling Beyond 0.35  m (the figures in this lecture are from André DeHon [1])

3. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 3 Confusion about Architecture l Confusion over Wild Claims » 10x – 1000x benefit, penalty » Area, Throughput, Energy/Power » Example: SPLASH-2 (FPGA): 6x faster than custom logic!!! l Should we drop ASICs and use FPGA’s? l How do we know if one architecture is really better than another?

4. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 4 Clearing up the Confusion l STEP 1: Implement computation each way l STEP 2: Assess results l STEP 3: Generalize lessons l Today’s talk is about step 2

5. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 5 Computational Efficiency Metrics l Definition: MOPS » Millions of algorithmically defined arithmetic operations (e.g. multiply, add, shift) – in a GP processor several instructions per “useful” operation l Figures of merit » MOPS/mW - Energy efficiency (battery life) » MOPS/mm 2 - Area efficiency (cost) Optimization of these “efficiencies” is the basic goal assuming functionality is met

6. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 6 Types of Scaling l Fixed-Voltage Scaling [3]: » Dimensions are scaled, supply-voltage and threshold voltages held constant » Used for technology generations > 0.6 μm l Constant Electric-Field (or “Full”) Scaling [3]: » Dimensions, supply-voltage, and threshold-voltages are scaled » Used for technology dimensions from 0.6 μm to 0.090 μm » Approach used by this lecture l General Scaling [3]: » Dimensions scaled by a different factor than supply-voltages and threshold voltages » Necessary because leakage becomes a problem if voltages continue to scale at the same rate » Will probably needed to accurately compare devices smaller than 0.090 μm

7. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 7 Common Supply Voltages Feature SizeSupply Voltages > 0.6 μm5 V 0.6 μm5 V – 3.3 V 0.35 μm3.3 V – 2.5 V 0.25 μm2.5 V – 1.8 V 0.18 μm1.8 – 1.2 V 0.13 μm1.2 – 1.0 V 0.090 μm1.0 – 0.9 V 0.065 μm? (assume ~0.65 V) 0.045 μm? (assume ~0.45 V)

8. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 8 Today’s Lecture l Introduction Scaling down to 1.0  m Scaling from 1.0  m down to 0.35  m Scaling from 0.6  m to 0.35  m Scaling Beyond 0.35  m (the figures in this lecture are from André DeHon [1])

9. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 9 Scaling down to 1.0  m l Premise: features scale “uniformly” » everything gets better in a predictable manner l Parameters: »λ (lambda) = 1/2 Tg – Mead and Conway » S – Bohr » 1/  – Dennard

10. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 10 Feature Size

11. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 11 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox )

12. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 12 Effects? l Area l Capacitance l Current (I d ) Gate Delay (  gd ) l Dynamic Power l Static Power

13. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 13 Area  →   L * W  →    m  m l 50% area l 2x capacity same area

14. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 14 Area Perspective

15. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 15 Capacitance l Capacitance per unit area » C ox =  SiO 2 /T ox » T ox →  T ox /  » C ox →  C ox

16. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 16 Capacitance l Gate Capacitance » C gate = A*C ox »A  →  A   » C ox →  C ox » C gate →  C gate / 

17. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 17 Current l Saturation Current » I d =(  C OX /2)(W/L)(V gs -V TH ) 2 » V gs= V →  V » V T →  V T » W →  W  » L →  L  » C ox →  C ox » I d →  I d

18. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 18 Gate Delay  gd =Q/I=(CV)/I V →  V I d →  I d C →  C /   gd →  gd /  

19. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 19 Power Dissipation (Dynamic) l Capacitive (Dis)charging » P=CV 2 f » V →  V » C →  C /  l Increase Frequency » f →   f l Power scaling » P →  P

20. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 20 Power Dissipation (Static) l Static Power » P=V*I » V →  V » I d →  I d » P →  P

21. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 21 Effects for Scaling down to 1.0μm Area 1/   Capacitance 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/   Dynamic Power  Static Power  Power Density (P/A)  

22. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 22 Today’s Lecture l Introduction Scaling down to 1.0  m Scaling from 1.0  m down to 0.35  m Scaling from 0.6  m to 0.35  m Scaling Beyond 0.35  m (the figures in this lecture are from André DeHon [1])

23. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 23 Current (Short-Channel) l I use this model for scaling below 1.0 μm l Saturation Current » » V GS, V DS =V →  V » V T →  V T » W →  W  » L →  L  » C ox →  C ox » I d →  I d

24. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 24 Gate Delay  gd =Q/I=(CV)/I V →  V I d →  I d C →  C /   gd →  gd / 

25. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 25 Power Dissipation (Dynamic) l Capacitive (Dis)charging » P=CV 2 f » V →  V » C →  C /  l Increase Frequency » f →  f l Power scaling » P →  P

26. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 26 Power Dissipation (Static) l Static Power » P=V*I » V →  V » I d →  I d » P →  P

27. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 27 Effects for Scaling Scaling MethodFixed-Voltage Feature-size range (μm)> 1.01.0-0.6 Area 1/   Capacitance 1/  Current (I d ) 1/  1 Gate Delay (  gd )1/   1/  Dynamic Power  1 Static Power  1 Power Density (P/A)  

28. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 28 Today’s Lecture l Introduction Scaling down to 1.0  m Scaling from 1.0  m down to 0.35  m Scaling from 0.6  m to 0.35  m Scaling Beyond 0.35  m (the figures in this lecture are from André DeHon [1])

29. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 29 Scaling l Problem: Power Density l Solution: Scale Voltages Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltages (V)

30. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 30 Current l Saturation Current » » V GS, V DS =V →  V  » V T →  V T  » W →  W  » L →  L  » C ox →  C ox » I d →  I d 

31. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 31 Gate Delay  gd =Q/I=(CV)/I V →  V  I d →  I d  C →  C /   gd →  gd / 

32. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 32 Power Dissipation (Dynamic) l Capacitive (Dis)charging » P=CV 2 f » V →  V /  » C →  C /  l Increase Frequency » f →  f l Power scaling » P →  P /  

33. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 33 Power Dissipation (Static) l Static Power » P=V*I » V →  V /  » I d →  I d /  » P →  P /  

34. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 34 Effects for Scaling Scaling MethodFixed-VoltageConst. El. Field Feature-size range (μm)> 1.01.0-0.60.6-0.35 Area 1/   Capacitance 1/  Current (I d ) 1/  1 Gate Delay (  gd )1/   1/  Dynamic Power  1 1/   Static Power  1 1/   Power Density (P/A)   

35. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 35 Today’s Lecture l Introduction Scaling down to 1.0  m Scaling from 1.0  m down to 0.35  m Scaling from 0.6  m to 0.35  m Scaling Beyond 0.35  m (the figures in this lecture are from André DeHon [1])

36. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 36 Capacitance Revisited Not necessarily C →  C/  l Ho, Mai, Horowitz → sidewall capacitance limited to 75% of total For technologies below 0.35 um assume C →  C /(  » Taken from Table 5 » assumes Miller effect

37. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 37 Scaling past 0.35  m

38. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 38 Scaling past 0.35  m FO4 delay = 500ps * Lg (linear,  gd →  gd /  ) Ho, Mai, Horowitz [2] → continue to 0.035  m l Assume V = 10V * Lg

39. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 39 Power Dissipation (Dynamic) l Capacitive (Dis)charging » P=CV 2 f » V →  V  » C →  C /(  (below 0.35  m) l Increase Frequency » f →  f l Power scaling » P →  P  (    (below 0.35  m)

40. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 40 Effects for Scaling Scaling MethodFixed-VoltageConst. El. Field Feature-size range (μm)> 1.01.0-0.60.6-0.35< 0.35 Area 1/   Capacitance 1/  1/(0.78  Current (I d ) 1/  1 Gate Delay (  gd )1/   1/  Dynamic Power  1 1/   1/(0.78    Static Power  1 1/   Power Density (P/A)   

41. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 41 Example #1: Multiply

42. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 42 Example #2: l Assumes gate delay dominates l If RC delay dominates, need to use a different approach AreaThroughput (Cell-updates / sec.) Area efficiency Lg (  m) Orig.Scaled To 0.13  m Orig.Scaled To 0.13  m MOPS/mm 2 Custom 2.0  m 270 mm 2 1.14 mm 2 500.0M 15380.0M13490.0 SPLASH-2 0.6  m 3870 mm 2 182.00 mm 2 3000.0M13840.0M3.58 Sparc10 0.4  m 64 mm 2 6.76 mm 2 1.2M3.7M0.55 DNA Sequence Matching

43. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 43 Example #3: MPEG-4 Encoding l Assumes gate delay dominates l If RC delay dominates, need to use a different approach Throughput (QCIF frames/sec.) PowerEnergy efficiency Lg (  m) VDDOrig.Scaled To 0.13  m, 1.3 V OrigScaled To 0.13  m OPS/mW Takahashi 0.3  m 2.5 V1027.760 mW14.4 mW1.92 Hashimoto 0.18  m 1.8 V1520.890 mW60.1 mW0.346

44. Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 44 References [1] A. DeHon, “Configurable Computing: Technology and Applications,” Proceedings of the SPIE, vol. 3526, Nov. 2-3 1998. [2] R. Ho, K. W. Mai, and M. A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, Apr. 2001 [3] J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2 nd Edition, Prentice Hall, 2003.