1. ENG241 Digital Design Week #4 Combinational Logic Design

2. 2 Resources  Chapter #4, Mano Sections 4.1 Combinational Circuits 4.3 Decoding 4.4 Encoding 4.5 Multiplexers 4.6 Comb Function Implementations

3. 3 Week #4 Topics  Decoders Combinational circuit Implementation  Encoders Priority Encoders  Multiplexers Combinational Circuit Implementation  Demultiplexers

4. Address Decoding 4 Device #1 Device #2 Device #3 Device #4 Control Unit 4 devices to put info on a Bus  I have 4 devices to put info on a Bus only one device  I must have only one device active at a time! only 2 wires  But! I have only 2 wires from my control unit BUS

5. 5 Decoders  Are circuits with n inputs and 2 n outputs  Drives high the output corresponding to binary code of input  Several Applications: Address Decoding, … A D0D0 D1D1

6. 6 2-to-4 Line Decoder  Notice they are minterms

7. 7 Other Decoders Example: 3-to-8 Line Decoder 4-to-16 Line Decoder 3 8 Binary to Octal Binary to Octal, Binary to Hex Binary to Hex, e.t.c

8. 8 Truth Table, 3-to-8 Decoder  Notice they are minterms Binary to Octal Example: Binary to Octal, Binary to Hex, e.t.c

9. 9 3-to-8 Line Decoder Schematic

10. 10 2-to-4 with Enable Why use an Enable?

11. 11 Enable Used for Expansion

12. 12 Usage for Decoders  Binary to Octal/Hex converters. Selecting memory banks, for example 4 memory banks can be selected individually using 2 address lines. Selecting memory banks, for example 4 memory banks can be selected individually using 2 address lines.  Implementing logic circuits!  Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.

13. 1. Address Decoding 13 Memory Bank #1 Memory Bank #2 Memory Bank #3 Memory Bank #4 CPU

14. 14 Decoder generates appropriate minterm based on control signals (it "decodes" control signals) 2. Decoders as General-purpose Logic  n:2 n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function

15. 15 Decoders as General-purpose Logic  Example: Implement the following Boolean functions 1. S(A 2,A 1,A 0 ) = SUM(m(1,2,4,7)) 2. C(A 2,A 1,A 0 ) = SUM(m(3,5,6,7)) 1.Since there are three inputs, we need a 3-to-8 line decoder. 2.The decoder generates the eight minterms for inputs A 0,A 1,A 2 3.An OR GATE forms the logical sum minterms required.

16. 16 Decoders as General-purpose Logic S(A 2,A 1,A 0 ) = SUM(m(1,2,4,7)) S

17. 17 Decoders as General-purpose Logic C(A 2,A 1,A 0 ) = SUM(m(3,5,6,7)) C

18. 18 F1 Example  F1 = A' B C' D + A' B' C D + A B C D AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 DEC Enable CD

19. 19Encoder  Encoder is the opposite of decoder 2 n inputs (or less – maybe BCD in) n outputs  Examples: Octal to binary conversion Hexadecimal to binary conversion

20. 20 Octal to Binary Encoder

21. 21 Design of Encoder A 0 = D 1 + D 3 + D 5 + D 7

22. 22 Multiplexer (or Mux)  Selects  Selects one of a set of inputs to pass on to output  For Every 2 n inputs we need n select lines  Applications: Useful for choosing from sets of data Memory or register to ALU MUX In0 In1 In2 In3 Out S0S0 S1S1

23. 23 2-Input Multiplexer

24. 24 4-to-1 Line Multiplexer

25. 25 Quad 2-to-4 Line Mux  Select one set of 4 lines

26. 26 C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 F Muxes as General-purpose Logic  2 n :1 multiplexer implements any function of n variables 1. With the variables used as control inputs and 2. Data inputs tied to 0 or 1 3. In essence, a lookup table  Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC

27. 27 ABCF00010010010101101000101011011111ABCF00010010010101101000101011011111 C' C' 0 1 AB S1S0 F 01230123 4:1 MUX C' C' 0 1 F C AB 0123456701234567 1010001110100011 S2 8:1 MUX S1S0  2 n-1 :1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement  Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC Muxes as General-purpose Logic

28. 28Demultiplexer  Takes one input out to one of 2 n possible outputs

29. 29 Revisiting Encoder!! Why?  Only ONE input is allowed to be active at a time!

30. 30 What’s the Problem?  What if D3 and D6 both high?  Simple OR circuit will set A to 111  This is an issue!!!!  Solution?

31. 31 Priority Encoder  Chooses one with highest priority Largest number, usually  “X” in input == 0 or 1 compact compact Truth Table

32. 32 Unfolding the Compact Truth Table D3D2D1D0A1A0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 What if all inputs are zero?

33. 33 Need Another Output!  A Valid Output!

34. 34 Expanded Truth Table (A 0 ) D3D2D1D0A0 0000X 00010 00101 00111 01000 01010 01100 01110 10001 10011 10101 10111 11001 11011 11101 11111 x011 0000 1111 1111 000111 10 00 01 11 10 D3D2D3D2 D1D0D1D0 A 0 = D 3 + D 2 D 1

35. 35 Valid is OR of all inputs

36. 36 entity dec_2_to_4 is port ( A 0, A 1 : in std_logic; D 0, D 1, D 2, D 3 : out std_logic); end entity dec_2_to_4; entity dec_2_to_4 is port ( A 0, A 1 : in std_logic; D 0, D 1, D 2, D 3 : out std_logic); end entity dec_2_to_4; Decoder: (VHDL  Data Flow) Example: 2-to-4 decoder D0D0 D1D1 D2D2 D3D3 A(1) A(0) Interface A 0_n A 1_n architecture dataflow1 of dec_2_to_4 is Signal A 0_n, A 1_n : std_logic; begin A 0_n <= not A 0 ; A 1_n <= not A 1 ; D 0 <= A 0_n and A 1_n ; D 1 <= A 0 and A 1_n ; D 2 <= A 0_n and A 1 ; D 3 <= A 0 and A 1 ; end architecture dataflow1; architecture dataflow1 of dec_2_to_4 is Signal A 0_n, A 1_n : std_logic; begin A 0_n <= not A 0 ; A 1_n <= not A 1 ; D 0 <= A 0_n and A 1_n ; D 1 <= A 0 and A 1_n ; D 2 <= A 0_n and A 1 ; D 3 <= A 0 and A 1 ; end architecture dataflow1; Functionality

37. 37 mux: Y <= D 0 when S 1 = ‘0’ and S 0 = ‘0’ else D 1 when S 1 = ‘0’ and S 0 = ‘1’ else D 2 when S 1 = ‘1’ and S 0 = ‘0’ else D 3 ; When Else Statement

38. 38 entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; Decoder: Data Flow #2 Example: 2-to-4 decoder D(0) D(1) D(2) D(3) A(1) A(0) Interface Functionality A(1..0)D(3..0) 000001 010010 100100 111000

39. 39 Dataflow VHDL Description of 4-to-1 Multiplexer -- 4-to-1 Line Mux; Conditional Dataflow VHDL Descrip library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1 is port (S: in std_logic_vector(1 downto 0); I: in std_logic_vector(3 downto 0); Y: out std_logic; end multiplexer_4_to_1;

40. 40 Cont.. Dataflow VHDL Description architecture function_table of multiplexer_4_to_1 is -- Using When Else Begin Y <= I(0) when S = “00” else I(1) when S = “01” else I(2) when S = “10” else I(3) when S = “11” else `X’; end function_table;

41. 41 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral (algorithmic) Registers State machines Test benches Sequential statements Subset most suitable for synthesis

42. 42 Structural VHDL Description of 2-to-4 Line Decoder

43. 43 Structural VHDL Description “Entity Declaration” -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;

44. 44 Structural VHDL Description (Signals) A0_n A1_n N0 N3 N1 N2

45. 45 Structural VHDL Description (Components) architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component;

46. 46 Structural VHDL Description (Connecting components) architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 declaration signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); …… end structural_1; A0_n A1_n component NOT1 port(in1: in std_logic; out1: out std_logic); end component;

47. 47 Structural VHDL Description (Connecting components) architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 declaration signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;

48. 48 2-to-4 Line Decoder: Complete Design architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1; A0_n A1_n -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;

49. 49

50. 50 Logic is Decoder Plus ….

51. 51 Compare the two Diagrams!

52. 52 Demux is a Decoder  With an enable

53. 53 Decoder Expansion  A 2-to-4 Line decoder requires 4 (2-input) AND gates  A 3-to-8 line decoder requires 8 (3-input) AND gates  If we want to design a 6-to-64 line decoder then we will need?  64 (6-input) AND gates!  Unfortunately, as decoders become larger, this approach gives a high gate input count!  Instead we will resort to a procedure that uses design hierarchy to construct any decoder with n inputs and 2 n outputs.  The resulting decoder should have the same or a lower gate input count than the one constructed simply enlarging each AND gate.

54. 54 Decoder Expansion To design a 3-to-8 line decoder (n=3) we can use a 2-to-4 line decoder and 1- to-2 line decoder feeding eight 2-input AND gates to form the minterms instead of using eight 3- input AND gates!

55. 55 General Procedure 1. Let k=n. 2. If k is even, divide k by 2 to obtain k/2. 3. Use 2 k AND gates driven by two decoders of output size 2 k/2. 4. If k is odd, obtain (k+1)/2 and (k-1)/2. 5. Use 2 k AND gates driven by a decoder of output size 2 (k+1)/2 and a decoder of output size 2 (k-1)/2 1. For each decoder resulting from step (2-3) (4-5), repeat with values obtained in step 2 until k=1. 2. For k=1, use a 1-to-2 decoder.

56. 56 Decoder Expansion - Example 1  3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal  (k+1)/2  2-to-4-line decoder  (k-1)/ 2  1-to-2-line decoder 2-to-4-line decoder  Number of output ANDs = 4  Number of inputs to decoders driving output ANDs = 2  Closest possible split to equal Two 1-to-2-line decoders  See next slide for result

57. 57 Decoder Expansion - Example 1  Result

58. 58 Multi-Level 6-to-64

59. 59 Aside: K Map for A 0  X on input means we must satisfy for both possibilities: 0, 1

60. 60 Variations  At right Enable not Inverted outputs

61. 61 Variations

62. 62 Structural VHDL Description of 4-to-1 Line Multiplexer N(0:3)D(0:3) S_n(0:1)

63. 63 Cont.. Structural VHDL Description of 4-to-1 Multiplexer -- 4-to-1 Line Multiplexer; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1_st is port (S: in std_logic_vector(0 to 1); I: in std_logic_vector(0 to 3); Y: out std_logic; end multiplexer_4_to_1_st;

64. 64 Cont.. Structural VHDL Description of 4-to-1 Multiplexer architecture structural_2 of multiplexer_4_to_1_st is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component; component OR4 port(in1, in2, in3, in4: in std_logic; out1: out std_logic); end component;

65. 65 Cont.. Structural VHDL Description of 4-to-1 Multiplexer architecture structural_2 of multiplexer_4_to_1_st is -- component NOT1 AND2 OR4 declarations signal S_n : std_logic(0 to 1); signal D, N : std_logic_vector(0 to 3); begin g0: NOT1 port map (S(0), S_n(0)); g1: NOT1 port map (S(1), S_n(1)); g2: AND2 port map (S_n(1), S_n(0), D(0)); g3: AND2 port map (S_n(1),S(0), D(1)); g4: AND2 port map (S(1),S(0), D(3)); g5: AND2 port map (S(1), S(0), D(3)); g6: AND2 port map (D(0), I(0), N(0)); g7: AND2 port map (D(1),I(1), N(1)); g8: AND2 port map (D(2),I(2),N(2)); g9: AND2 port map (D(3),I(3), N(3)); g10: OR4 port map (N(0), N(1), N(2), N(3), Y); end structural_2;