1. Implementation of Infomax ICA Algorithm with Low-Power Analog CMOS Circuits Ki-Seok Cho and Soo-Young Lee Brain Science Research Center and Department of Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology

2. 2 Why Analog Infomax-ICA Chip?  Advantages – Massive Parallel Processing – Low power Consumption – Simple Architecture  Related Researches – ICA chip using Herault-Jutten algorithm 1992, Cohen & Andreas Current mode sub-threshold MOS implementation Convergence is sensitive to the mixing condition – Infomax ICA algorithm is less sensitive to the mixing condition than Herault-Jutten one

3. 3 Used Algorithm  Instantaneous Mixture – Linear & no delayed mixture  Maximize Entropy with Natural Gradient –

4. 4 Architecture   multiplier   current summation r  learning rate 4 x 4 ICA network in one Chip

5. 5 Test Results in Waveforms Source Signals (s1, s2) two different male’s voice 16 kHz sampled Mixed Signals (x1, x2) Instantaneous mixture Mixing Mtx A is Separated Signals (o1, o2) Recovered original sources

6. 6 Test Results in SNRs X1X2O1O2 S10.82.8-3.637.5 S23.91.510.1-1.5 source[n]  a sampled source signal result[n]  a sampled mixed signal or separated signal n  iteration number SNRs in dB

7. 7 Fabricated Chip 2.8mm x 2.8mm AMS CMOS 0.6um 2 poly-3 metal Analog Digital Hybrid Process Die Photo of a Fabricated ICA Chip

8. 8 Advantages of Proposed Chip Modular Structure: Can be extended to any size network All-in-One chip: Does not need any DSP nor AD/DA converter High Speed: Massive parallel processing is possible Chip1 Chip2 Chip N...

9. 9 Discussion Some Problems Did not consider the density of circuits Only for Super-Gaussian source case We could test only 2x2 case because of offsets Further Works Sub-threshold circuits Can be applied to Sub-Gaussian case Simple network using 1-Q multiplier Need noise-robust circuits

10. 10 Adding Bias & Shifting Adding Bias Wo For Positive Input z Shifting of non-linear Function For Positive u

11. 11 Positive Weight Network z1 z2 z3  (x1+x2+x3) u1 u2 u3  (u) wp11 wp21 -- -- wo1 wo3 wo2

12. 12 Nonholonomic ICA In the 2 x 2 network Using Nonholonomic ICA

13. 13 I1 I2 M1 M2 M3 I3 Io I4 I3 M4 M5 Triple Input 1-Q multiplier