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LOGO Ultralow-Power Design in Near-Threshold Region Prof. : M. Shams Name: Yiqi Chang Student #:6624968.

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Presentation on theme: "LOGO Ultralow-Power Design in Near-Threshold Region Prof. : M. Shams Name: Yiqi Chang Student #:6624968."— Presentation transcript:

1 LOGO Ultralow-Power Design in Near-Threshold Region Prof. : M. Shams Name: Yiqi Chang Student #:6624968

2 LOGO Outline Introduction 1 Device and Circuit model 2 Sensitivity Analysis 3 Energy-Delay Optimization 4 Sense-Amplifier-Based PTL (SAPTL) 5 Architectural Optimization 6 Conclusion 7

3 LOGO Introduction Question: Why we need ultralow power? What is near-threshold region?

4 LOGO Introduction Past five years minimum- energy point (MEP) Traditional minimum-delay operational point (MDP) Optimization logic circuit

5 LOGO Introduction Fig. 1. pareto-optimal design curve Energy-delay trade-off in combinational logic.

6 LOGO Introduction Use minimum-energy point Voltage-based optimization Various architectural techniques Ultralow power design Method to get ultralow power

7 LOGO Device and Circuit model Current model: Current of starting point (VGS =VT) : n: subthreshold slope, μ: mobility, Cox: oxide capacitance, and thermal voltage ϕ t =kT/q Current in the vicinity of VT: IC: inversion coefficient, and k fit is model-fitting parameter

8 LOGO Device and Circuit model inversion coefficient: the degree of inversion of the transistor sub-V T (IC 1)

9 LOGO Device and Circuit model Fig. 2 Inversion coefficient for HV T and LV T devices for a 65 nm technology.

10 LOGO Device and Circuit model Delay Model:

11 LOGO Device and Circuit model Energy Model:

12 LOGO Sensitivity Analysis gate sizing supply voltage threshold voltage energy-delay trade-offs

13 LOGO Sensitivity Analysis Sensitivity: a parameter x represents a percent reduction in energy for a percent increase in delay

14 LOGO Sensitivity Analysis

15 LOGO Sensitivity Analysis Formulas of S:

16 LOGO Sensitivity Analysis Good news for MEP region Easier to do than to adjust gate sizing. Not require any layout changes Could be done after chip fabrication

17 LOGO Energy-Delay Optimization 3 parameters for optimization: Supply Sizing V T (selected from the available discrete values)

18 LOGO Energy-Delay Optimization

19 LOGO Energy-Delay Optimization

20 LOGO Energy-Delay Optimization Make V T is variable for different regions of energy-delay cure

21 LOGO Sense-Amplifier-Based PTL (SAPTL) How to make V T various?

22 LOGO Sense-Amplifier-Based PTL (SAPTL) PTL no path from VDD to gnd

23 LOGO Sense-Amplifier-Based PTL (SAPTL) D active : sum of the sense amplifier and driver delays D stack : the stack delay

24 LOGO Sense-Amplifier-Based PTL (SAPTL) www.themegallery.com

25 LOGO Architectural Optimization Some architectural can be used to get optimization Time-multiplexing technique www.themegallery.com

26 LOGO Architectural Optimization Pipelining for feedback time-multiplexed logic www.themegallery.com

27 LOGO Conclusion 1.MEP: expensive of performance. 2.MDP: expensive of energy. 3.Energy 20%↑ → 10-times in performance↑ 4.PTL outperforms standard CMOS in the near- threshold region(achieving lower energy). 5.The use of time-multiplexing: both lower area and energy without performance penalty (reduced leakage that comes with a lower area).

28 LOGO

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