2. Mid Semester A Project Presentation Instructor: Mr. Almog Assaf Real Time Image Processing Presented by: Baruch Koren Shahaf Fisher Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

3. Agenda Project ’ s Goals. Project ’ s Goals. System Block Diagram and System overview. System Block Diagram and System overview. Defining DVI interface and generic blocks. Defining DVI interface and generic blocks. Image Processing Background- Color Spaces. Image Processing Background- Color Spaces. Image Processing Development Stages. Image Processing Development Stages. Time table. Time table. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

4. Project ’ s Goals Preparing a systematic infrastructure for future laboratories projects. Preparing a systematic infrastructure for future laboratories projects. Preparing instructions for integrating new components to this system. Preparing instructions for integrating new components to this system. Studying this complex system - the environment and the designing tools. Studying this complex system - the environment and the designing tools. Studying VHDL language, with an emphasis on coding style, modular and generic design. Studying VHDL language, with an emphasis on coding style, modular and generic design. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

5. Project ’ s Goals Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems. Studying and implementing topics in image processing, especially algorithms that can be implemented in real time video systems. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

6. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

7. System Overview DVI interfaces. DVI interfaces. System Clocks. System Clocks. Generic modules. Generic modules. Gidel interface. Gidel interface. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

8. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

9. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

10. DVI interfaces Connection between the DVI Reciever and Transmitter to the FPGA ’ s top level hierarchy. Connection between the DVI Reciever and Transmitter to the FPGA ’ s top level hierarchy. Settings for using default DVI Receiver (SiI1171) operation mode: Settings for using default DVI Receiver (SiI1171) operation mode:  not programmable - with no I2C involve  24-bit pixel data for one pixel per clock Settings for using default DVI Transmitter (SiI1172) operation mode: Settings for using default DVI Transmitter (SiI1172) operation mode:  not programmable - with no I2C involve.  samples one-half pixel (12 bit) at every latch falling and rising edge of the clock. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

11. Before DVI interfaces Before DVI interfaces DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx CLK i 2 c and control 24bit 12bit i 2 c and control

12. After DVI interfaces After DVI interfaces DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 24bit 12bit DVI_interface_2rx 24bit

13. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

14. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

15. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs

16. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs

17. System Clocks Input Clocks: Input Clocks:  Main clock (clk0,clk1).  Local bus clock (lclk).  Slower clock (clk2). System PLLs: System PLLs:  pll4ddr2.  user_pll. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

18. Generic modules Generic block type 1 Generic block type 1 Generic block type 2 Generic block type 2 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

19. Defining Generic block type 1 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory vsync_out Clk data_en_in vsync_in hsync_in data_in(23 DOWNTO 0) 1 data_out(23 DOWNTO 0) data_en_out hsync_out

20. Integrating Generic block type 1 DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control data_en_in vsync_in hsync_in data_in DVI_interface_2tx Clk 1 Clk vsync_out data_out data_en_out hsync_out block1DVI_interface_2rx 24bit 12bit

21. Defining Generic block type 2 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory read_req Write_en 2 data_out Controller read_en 2 data_out Write_reqWrite_req Write_enWrite_en Write_req data_in data_in Clk Clk syncs_insyncs_insyncs_outsyncs_out

22. Generic block type 2 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory read_req Write_en data_out read_en Write_req data_in Clk Buffer (FIFO) X X X X X X X X X X X X Example Use of block type 2 … … … syncs_in syncs_out

23. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

24. System Top Hierarchy Block Diagram DVI input DVI Output RXTX qe_rx Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory de_rx hsync_rx odck_rx vsync_rx idck_tx de_tx vsync_tx hsync_tx data_tx i 2 c and control DVI_interface_2tx 1 block1 24bit 12bit DVI_interface_2rx DVI_interface_2rx 11 data_en_in vsync_in hsync_in data_in Clk 24bit Clk vsync_out data_out data_en_out hsync_out block1block1 Gidel ’ s block top_if 24bit clk1 clk0 Local Bus External ddrII Memoryinterface pll4ddrI I user_pl l clk clk_plus clk_minus ck_a ck_b

25. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Block Diagram and Ports Gidel Interface

26. Image Processing Background- Color Spaces Definition: is a mathematical way of specifying the color of a pixel in a color image. A color space is a mathematical way of specifying the color of a pixel in a color image. Objective: convert our video input to a color space which suits best image processing algorithms. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

27. Color Spaces-RGB RGB model uses three numerical components to represent a color in a three-dimensional Cartesian coordinate system. RGB model uses three numerical components to represent a color in a three-dimensional Cartesian coordinate system. Each component has a range Each component has a range of 0 to 255 (for a 8-bit of 0 to 255 (for a 8-bit representation per color). representation per color). Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

28. RGB is an additive color system and that is why RGB color space is the most common choice for computer graphics and image and video displayers. RGB is an additive color system and that is why RGB color space is the most common choice for computer graphics and image and video displayers. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Color Spaces-RGB

29. Incompatibility of RGB space to Image Processing processing an image in the RGB space is more complex. processing an image in the RGB space is more complex. Using RGB requires wider bandwidth and larger storage space. Using RGB requires wider bandwidth and larger storage space. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

30. Which Color Space Suits Best Image Processing Algorithms? The human Eye is much more sensitive to intensity changes than to colors. The human Eye is much more sensitive to intensity changes than to colors. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Most image processing algorithms operates on the image intensity. If we use a color space which does a separation between intensity component and chrominance components, Image processing algorithms will be faster, demand less bandwidth and less storage space, and cheaper.

31. Color Spaces-YCbCr The YCbCr is a model which does a separation between intensity (luma) component (component Y) and chrominance components (Cb,Cr). Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

32. Color Spaces-YCbCr The basic equations to convert between gamma-corrected RGB (notated as R ’ G ’ B ’ ) and YCbCr are: The basic equations to convert between gamma-corrected RGB (notated as R ’ G ’ B ’ ) and YCbCr are: Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

33. Development Stages Background Background Design Design Coding Coding Simulation Simulation Integration & Implementation Integration & Implementation Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

34. Development Stages - Simulation Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory SIM.UUTANA. Files In Files Out Test Bench

35. WeekDatesActionComments 1-2 5.11.06 - Introduction to the Lab, comprehending and defining the project goals. 18.11.06 3 19.11.06 - Studying the understanding the complex system and its designing tools available. 25.11.06 4 26.11.06 - Preparing and presenting the characterization report. Project Characterization Presentation 2.12.06 5 3.12.06 - Preparing a detailed blocks diagram of the system. 9.12.06 Time Table Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

36. WeekDatesActionComments 6 10.12.06 - Defining and characterizing the abstract generic block, which will be implemented when defining a processing block. 16.12.06 7-10 17.12.06 - Preparing and presenting the Midterm Presentation and report. Defining the memory and the display controllers interfaces. Midterm Presentation 13.01.07 11 14.01.07 - Studying and writing background on the meaning of color spaces and converting between color spaces needed for processing algorithms Designing a Basic processing unit – color spaces converter. 20.01.07 12-13 21.01.07 - VHDL coding of the Basic processing unit – color spaces converter. 3.02.07 Time Table Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

37. Time Table WeekDatesActionComments 14 04.02.07 - Simulation of the Basic processing unit – color spaces converter. 10.02.07 15- End SemA 11.02.07 - Integration and Implementation of the Basic processing unit – color spaces converter. Preparing and presenting the semester A Project Presentation and report. Exams period Final A semester Project Presentation 06.03.07 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory

38. THE END!

39. Auxiliary slides

40. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory Basic System Block Diagram and Ports

41. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory --====================================================================== --= DVI Transmitter connections (on PSDB_DVI) = --====================================================================== data_tx : OUT STD_LOGIC_VECTOR( 11 DOWNTO 0 ); -- Transitter data output msen_tx : IN STD_LOGIC; -- Monitor Sense pd_tx : OUT STD_LOGIC; -- Power Down (Active Low) de_tx : OUT STD_LOGIC; -- Data Enable hsync_tx : OUT STD_LOGIC; -- Horizontal Sync vsync_tx : OUT STD_LOGIC; -- Vertical Sync scl_tx : INOUT STD_LOGIC; -- I2C Clock sda_tx : INOUT STD_LOGIC; -- I2C Data idck_tx : OUT STD_LOGIC; -- Transmitter data clock isel_rst_tx : OUT STD_LOGIC; -- I2C Interface Select ctl3_tx : OUT STD_LOGIC; -- Transmitter Control Signal SiI1172 ports – DVI Transmitter

42. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory --====================================================================== --= DVI Receiver connections (on PSDB_DVI) = --====================================================================== qe_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver even data input qo_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver odd data input odck_rx : IN STD_LOGIC; -- Receiver data clock scdt_rx : IN STD_LOGIC; -- Sync detect ctl1_rx : IN STD_LOGIC; -- Receiver control signal ctl2_rx : IN STD_LOGIC; -- Receiver control signal ctl3_rx : IN STD_LOGIC; -- Receiver control signal stag_out_rx : OUT STD_LOGIC; -- Staggered Output pixs_rx : OUT STD_LOGIC; -- Pixel Select st_sda_rx : INOUT STD_LOGIC; -- I2C Data / Output Drive pd_rx : OUT STD_LOGIC; -- Power Down hs_djtr_rx : OUT STD_LOGIC; -- Horisontal Sync De-jitter ock_inv_scl_rx : INOUT STD_LOGIC; -- ODCK Polarity / I2C Clock mode_rx : OUT STD_LOGIC; -- Mode Select hsync_rx : IN STD_LOGIC; -- Horizontal Sync vsync_rx : IN STD_LOGIC; -- Vertical Sync de_rx : IN STD_LOGIC; -- Data Enable pdo_rx : OUT STD_LOGIC; -- Output driver power down hpd_rx : IN STD_LOGIC SiI1171 ports - DVI Receiver SiI1171 ports - DVI Receiver

43. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory --DVI Transmitter connections (on PSDB_DVI) pd_tx <= '1';-- de_tx <= de_rx;-- hsync_tx <= hsync_rx;-- vsync_tx <= vsync_rx;-- scl_tx <= '0';-- sda_tx <= '0';-- idck_tx <= odck_rx;-- isel_rst_tx <= '0';-- ctl3_tx <= '0';-- --DVI Receiver connections (on PSDB_DVI) stag_out_rx <= '1';-- pixs_rx <= '0';-- st_sda_rx <= '1';-- pd_rx <= '1';-- hs_djtr_rx <= '1';-- ock_inv_scl_rx <= '0';-- mode_rx <= '1';-- pdo_rx <= '1';-- SiI1171 and SiI1172 configuration SiI1171 and SiI1172 configuration Settings for using default Settings for using default DVI Transmitter operation mode DVI Transmitter operation mode not programmable - with no I2C involve not programmable - with no I2C involve samples one-half pixel (12 bit) at every samples one-half pixel (12 bit) at every latch falling and rising edge of the clock latch falling and rising edge of the clock Settings for using one pixel per clock Settings for using one pixel per clock DVI Receiver operation mode DVI Receiver operation mode not programmable - with no I2C involve not programmable - with no I2C involve 24-bit pixel data for one pixel per clock 24-bit pixel data for one pixel per clock

44. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory process(odck_rx)begin case odck_rx is when '0' => data_tx <= qe_rx ( 23 DOWNTO 12); when '1' => data_tx <= qe_rx ( 11 DOWNTO 0); end case; end process; Setting the data for the transmitter Setting the data for the transmitter

45. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Block Diagram and Ports

46. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System Clocks clk0,clk1: the GiDEL, PROCStar II ™ main clk that was set, enters 2 PLLs as follows: clk0: enters to pll4ddrII_a_1, reserved pll, which produces 2 differential clocks to the external memory DDR2 SDRAM 64MB banks: ck_a and ck_b for DDR2 bank A and B, respectfully. clk0: enters to pll4ddrII_a_1, reserved pll, which produces 2 differential clocks to the external memory DDR2 SDRAM 64MB banks: ck_a and ck_b for DDR2 bank A and B, respectfully. clk1: enters to the user PLL, and produces 3 output clocks. clk, clk_plus, clk_minus have the same frequency desired by the user, which can be chosen as an integer multiple of the main frequency – with respect to the the maximum value allowed 300Mhz. clk, clk_plus, clk_minus have phase shifting of 0 deg, +127 deg, -127 deg, respectfully. clk1: enters to the user PLL, and produces 3 output clocks. clk, clk_plus, clk_minus have the same frequency desired by the user, which can be chosen as an integer multiple of the main frequency – with respect to the the maximum value allowed 300Mhz. clk, clk_plus, clk_minus have phase shifting of 0 deg, +127 deg, -127 deg, respectfully. The GiDEL, PROCStar II ™ main clk (clk0,clk1) ranges from 30Mhz up to 200Mhz, and can be defined as desired. clk1 arrives ~200ps before clk0. In the example above main clk was set to 200Mhz.

47. Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory System CLOCKs lclk:This is the Local Bus Clock, working at 33Mhz. clk2: The GiDEL, PROCStar II ™ external or internal slower clk. If internal then can be chosen as one of the following values: Main clock * (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14, 1/16, 1/18, 1/20, 1/22, 1/24, 1/26, 1/28, 1/30, 1/32). For example when the main clock is 100Mhz then clk2 can be set as: (50, 25, 16.667, 12.5, 10, 8.3333, 7.1429, 6.25, 5.5556, 5, 4.5455, 4.1667, 3.8462, 3.5714, 3.3333, 3.125) [Mhz ]. The GiDEL, PROCStar II ™ uses the defult of Main clock * 1/8.

48. DVI_interface_rx2tx ports Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory ENTITY DVI_interface_rx2tx IS PORT( PORT(--====================================================================== --= DVI Transmitter connections (on PSDB_DVI) = --====================================================================== data_tx : OUT STD_LOGIC_VECTOR( 11 DOWNTO 0 ); -- Transitter data output msen_tx : IN STD_LOGIC; -- Monitor Sense pd_tx : OUT STD_LOGIC; -- Power Down (Active Low) de_tx : OUT STD_LOGIC; -- Data Enable hsync_tx : OUT STD_LOGIC; -- Horizontal Sync vsync_tx : OUT STD_LOGIC; -- Vertical Sync scl_tx : INOUT STD_LOGIC; -- I2C Clock sda_tx : INOUT STD_LOGIC; -- I2C Data idck_tx : OUT STD_LOGIC; -- Transmitter data clock isel_rst_tx : OUT STD_LOGIC; -- I2C Interface Select ctl3_tx : OUT STD_LOGIC; -- Transmitter Control Signal --====================================================================== --= DVI Receiver connections (on PSDB_DVI) = --====================================================================== qe_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver even data input qo_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver odd data input odck_rx : IN STD_LOGIC; -- Receiver data clock scdt_rx : IN STD_LOGIC; -- Sync detect ctl1_rx : IN STD_LOGIC; -- Receiver control signal ctl2_rx : IN STD_LOGIC; -- Receiver control signal ctl3_rx : IN STD_LOGIC; -- Receiver control signal stag_out_rx : OUT STD_LOGIC; -- Staggered Output pixs_rx : OUT STD_LOGIC; -- Pixel Select st_sda_rx : INOUT STD_LOGIC; -- I2C Data / Output Drive pd_rx : OUT STD_LOGIC; -- Power Down hs_djtr_rx : OUT STD_LOGIC; -- Horisontal Sync De-jitter ock_inv_scl_rx : INOUT STD_LOGIC; -- ODCK Polarity / I2C Clock mode_rx : OUT STD_LOGIC; -- Mode Select hsync_rx : IN STD_LOGIC; -- Horizontal Sync vsync_rx : IN STD_LOGIC; -- Vertical Sync de_rx : IN STD_LOGIC; -- Data Enable pdo_rx : OUT STD_LOGIC; -- Output driver power down hpd_rx : IN STD_LOGIC -- Hot Plug detection signal ); ); END DVI_interface_rx2tx;

49. Defining Generic block type 1 Technion – Israel Institute Of Technology Electrical Engineering Department High speed digital systems laboratory ENTITY block1 IS ENTITY block1 IS PORT( PORT(--====================================================================== --= block1 Inputs = --====================================================================== clk : IN STD_LOGIC; -- main clock from odck_rx data_in : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- data input de_in : IN STD_LOGIC; -- Data Enable input hsync_in : IN STD_LOGIC; -- Horizontal Sync input vsync_in : IN STD_LOGIC; -- Vertical Sync input --====================================================================== --= block1 Outputs = --====================================================================== -- ???clk_out : OUT STD_LOGIC; -- main clock out??? data_out : OUT STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- data output de_out : OUT STD_LOGIC; -- Data Enable output hsync_out : OUT STD_LOGIC; -- Horizontal Sync output vsync_out : OUT STD_LOGIC--; -- Vertical Sync output ); ); END block1; ARCHITECTURE arc_block1_In2Out OF block1 IS BEGIN -- ??? clk_out <=clk; data_out <=data_in; de_out <= de_in; hsync_out<=hsync_in; vsync_out<=vsync_in; END arc_block1_In2Out;