1. RB - EPFL/IC/LAP - A2008 1 FPGARM4U rene.beuchat@epfl.ch LAP/I&C/EPFL Chargé de cours LSN/EIG Prof. HES Filippo Rusco, Yorick Brunet

2. RB - EPFL/IC/LAP - A20082 Sections of the course  The last section introduces an ARM9 processor interfaced with the FPGA4U board by a proprietary bus. Linux is running on the ARM board and the FPGA is used as specific programmable interfaces.

3. RB - EPFL/IC/LAP - A20083 Schedule (4) 4 weeks  Embedded systems on FPGA and ARM processor  master interfaces C(8h) ARM family, ARM9 more specifically USB2 and microcontroller (FX2) L(8h)Multiprocessor System ARM/NIOS FPGARM4U / FPGA4U report & demo & presentation

4. RB - EPFL/IC/LAP - A2008 4 FPGARM4U Hardware design

5. RB - EPFL/IC/LAP - A20085 Hardware Design  When a new product is designed, the choice of the processor is a very difficult task.  Lot of processors are available on the market, and their life could be (very) short.  In the embedded world the ARM family is largely deployed  In this "single" family thousands of devices are proposed.  Overview of the family

6. RB - EPFL/IC/LAP - A20086 FPGARM4U-ARM family  ARM7, ARM9, ARM11 are hardcores processors  Cortex are synthesizable cores  30 MHz  2GHz clock FamilyLicenses Cortex TM 49 ARM11 TM 70 ARM9 TM 249 ARM7 TM 158 Ref.: http://www.arm.com/products/licensing/licencees.html

7. RB - EPFL/IC/LAP - A20087 FPGARM4U-ARM Cortex family

8. RB - EPFL/IC/LAP - A20088 FPGARM4U-ARM Cortex family ARM Cortex-A Series, applications processors for complex OS and user applications. Supports the ARM and Thumb-2 instruction sets. ARM Cortex-R Series, embedded processors for real-time systems. Supports the ARM and Thumb- 2 instruction sets. ARM Cortex-M Series, deeply embedded processors optimized for cost sensitive applications. Supports the Thumb-2 instruction set only.

9. RB - EPFL/IC/LAP - A20089 FPGARM4U Atmel Families

10. RB - EPFL/IC/LAP - A200810 FPGARM4U ARM9 DIOPSYS From: http://www.atmel.com/products/diopsis/overview.asp ARM9 + DSP engine, 10 floating p/cycles  >1G flop/s

11. RB - EPFL/IC/LAP - A200811 FPGARM4U Atmel mAgicV DSP

12. RB - EPFL/IC/LAP - A200812 FPGARM4U Architecture  AT91SAM9263  SDRAM 64MB: 2x16Mx16  Serial Flash 8MB  Ethernet 10/100 Mb/s  CAN Bus 2.0  RS-232 UART  I2C  2 USB Master FS  1 USB Slave FS (12 Mb/s)  SD/MMC/SDIO  JTAG Extension connector for FPGA4U Extension connectors for I/O

13. RB - EPFL/IC/LAP - A200813 FPGARM4U AT91SAM9263 ARM9E-S Technical Reference Manual (Rev 1) (290 pages, revision B, updated 4/08) http://www.atmel.com/dyn/resources/prod_documents/doc6178.pdf AT91SAM9263 Preliminary Summary (51 pages, revision FS, updated 9/08) http://www.atmel.com/dyn/resources/prod_documents/6249s.pdf AT91SAM9263 Preliminary (1097 pages, revision F, updated 9/08) http://www.atmel.com/dyn/resources/prod_documents/doc6249.pdf RevA : > 50 bugs RevB : > 40 bugs

14. RB - EPFL/IC/LAP - A200814 FPGARM4U AT91SAM9263

15. RB - EPFL/IC/LAP - A200815 FPGARM4U AT91SAM9263

16. RB - EPFL/IC/LAP - A200816 FPGARM4U AT91SAM9263  ARM 926EJ-S Core v5TE  3 instruction sets: 32-bit ARM instruction set used in ARM state 16-bit Thumb instruction set used in Thumb state 8-bit Java bytecode used in Jazelle state.  5 stage pipeline, Byte code Java (6 st. pipeline)  MAC (Mult-Acc) ARM 926EJ-S core: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/DDI0222.pdf

17. RB - EPFL/IC/LAP - A200817 FPGARM4U AT91SAM9263  Caches: Instruction 16 kBytes Data 16 kBytes  Fast internal TCM (Tightly Coupled Memory): SRAM 80kBytes  Internal Memories: 16 kBytes SRAM 128 kBytes ROM (monitor, boot)

18. RB - EPFL/IC/LAP - A200818 FPGARM4U AT91SAM9263

19. RB - EPFL/IC/LAP - A200819 FPGARM4U AT91SAM9263  Fast internal Tightly Coupled memory: SRAM 80kBytes, separated in 3 areas A, B, C Instruction TCM, Data TCM, Frame Buffer ITCM: The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR  Internal Memories: 16 kBytes SRAM 128 kBytes ROM (monitor, boot)

20. RB - EPFL/IC/LAP - A200820 FPGARM4U Boot Strategies  The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters.  REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has booted. (Refer to the section “AT91SAM9263 Bus Matrix” in the product datasheet for more details.)  When REMAP = 0, BMS allows the user to layout at address 0x0: If BMS = 1 @Reset, the boot memory is the embedded ROM. If BMS = 0 @Reset, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.  The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.

21. RB - EPFL/IC/LAP - A200821 FPGARM4U BMS = 1, Boot on Embedded ROM  The system boots on internal Boot Program. Boot at slow clock Auto baudrate detection Downloads and runs an application from external storage media into internal SRAM Downloaded code size depends on embedded SRAM size Automatic detection of valid application Bootloader on a non-volatile memory SD Card NAND Flash SPI DataFlash® and Serial Flash connected on NPCS0 of the SPI0 Interface with SAM-BA® Graphic User Interface to enable code loading via:  Serial communication on a DBGU  USB Bulk Device Port

22. RB - EPFL/IC/LAP - A200822 FPGARM4U BMS = 0, Boot on External Memory  Boot at slow clock  Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.  The customer-programmed software must perform a complete configuration.  To speed up the boot sequence when booting at 32kHz EBI0 CS0 (BMS=0) the user must: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and Start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value.

23. RB - EPFL/IC/LAP - A200823 FPGARM4U AT91SAM9263

24. RB - EPFL/IC/LAP - A200824 FPGARM4U Boot devices  Serial Flash memory  to receive Bootstrap program, need to be programmed before: Serial link and SAM-BA software  Then USB Key with an OS kernel as Linux  Or Network Ethernet NFS  Laboratory exercise

25. RB - EPFL/IC/LAP - A200825 FPGARM4U AT91SAM9263

26. RB - EPFL/IC/LAP - A200826 FPGARM4U Extension I/O  Many devices available as slaves: MultiMedia Card (2 channels) Timers (3x) PWM (4 channels), Pulse Width Modulation TWI (Serial i2c, 1x), Two Wire Interface SPI (Serial, 2x), Synchronous Programmable Interface SSC (Serial, 2x), Synchronous Serial Controller UART (3x), Universal Asynchronous Receiver/Transmitter CAN (1x) AC97 (Sound) USB (1 slave)

27. RB - EPFL/IC/LAP - A200827 FPGARM4U AT91SAM9263

28. RB - EPFL/IC/LAP - A200828 FPGARM4U Extension I/O  Many devices available as masters (DMA): Ethernet 10/100 USB Master (2x) LCD controller Image sensor 2D graphic controller 20 channels peripheral DMA 2 general DMA (external request)

29. RB - EPFL/IC/LAP - A200829 FPGARM4U AT91SAM9263

30. RB - EPFL/IC/LAP - A200830 FPGARM4U Extension Bus  2 External Bus Interface for memories or external programmable interfaces:  EBIO0, 6 Chip Select nCS0[0..5]: SDRAM SRAM ROM, EPROM, Flash Compact Flash NAND Flash (serial) ECC controller 8, 16, 32 bits data bus

31. RB - EPFL/IC/LAP - A200831 FPGARM4U Extension Bus  EBIO1, 3 Chip Select nCS1[0..2]: SDRAM SRAM ROM, EPROM, Flash NAND Flash (serial) ECC controller 8, 16, 32 bits data bus

32. RB - EPFL/IC/LAP - A200832 FPGA4U  FPGARM4U  An ARM processor is connected to a FPGA through an extension bus.  The ARM9 or an internal DMA unit are the masters of the transfers  A specific External Bus Interface is used: EBI1  The document explains the way to be able to realize a bridge in the FPGA for ARM9  Avalon transfers

33. RB - EPFL/IC/LAP - A200833 FPGARM4U FPGA4U internal Avalon interface  To interface the FPGA4U and the Avalon Bus, an EBI-Avalon (master) needs to be design:  Laboratory exercise : Search in the Datasheet the timing for EBI1 as 16 bits external memory for SRAM. Design an Avalon master receiving EBI1 as external requester of transfers. Realize it in VHDL, Implement it, Simulate it and … Test it.

34. RB - EPFL/IC/LAP - A200834 FPGARM4U EBI1 Bus  The EBI1 Bus is used with FPGA4U as interface for FPGA:  Addresses[22..0]  8 MBytes space  Data [15..0]  16 bits data bus  nCS0, nCS2  2 Chip Selects  nOE  Output Enable (Read)  nWr[1..0]  2 Write Select  nWAIT  Wait clk cycles requested

35. RB - EPFL/IC/LAP - A200835 FPGARM4U FPGA4U Bridge: internal Avalon interface AT91 SAM9263 FPGA-CycloneII AM Bridge NIOSII SDRAM Ctrl LCD Ctrl Avalon EBI1 Add, Ctrl nWAIT Data AS SDRAM LCD

36. RB - EPFL/IC/LAP - A200836 FPGARM4U FPGA4U Bridge: internal Avalon interface  The Bridge receives the Addr, Ctrl and transfers Data  It map the addresses from the EBI to an address to the Avalon bus  The bridge can be configured by the EBI1 with the nCS2 selection signal  The PageAddr register is added to the EBI1_Address to generate the Avalon Address

37. RB - EPFL/IC/LAP - A200837 FPGARM4U FPGA4U B ridge interface FPGA-CycloneII Bridge ARM WrNIOS Wr PageAddrSDRAM_start SDRAM_Lgth LCD_FrBuf LCD_Lgth PageAddr nWAIT nCS0 nCS2 As_CS + WaitRequest AM_Addr[31..0] EBI1_Addr[22..0]

38. RB - EPFL/IC/LAP - A200838 FPGARM4U FPGA4U B ridge interface 157 80 CS0 BaseAdd  CS0 LgtAdd PageAddr + 157 80 PageAddr  LgtAdd SDRAM 8MB window CS2 BaseAdd  SDRAM_start  SDRAM_Lgth LCD_FrBuf  PageAddr ARM memory space Avalon memory space

39. RB - EPFL/IC/LAP - A200839 FPGARM4U FPGA4U B ridge interface ARM WriteNIOS Write PageAddrSDRAM_start SDRAM_Lgth LCD_FrBuf LCD_Lgth  The Bridge is seen as a programmable interface from the ARM and the NIOSII  All the registers have to be readable by both processors

40. RB - EPFL/IC/LAP - A200840 FPGARM4U FPGA4U B ridge interface  The number of bits dedicated to the PageAddr and the adder specify the granularity of the address mapping 31242322161587430 011100000XXXXXXXXXXXXXXXXXXXXXXx ↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓ 000000000XXXXXXXXXXXXXXXXXXXXXXx ++++++++++++++++ PPPPPPPPPPPPPPPP↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓ YYYYYYYYYYYYYYYYXXXXXXXXXXXXXXXx H' 70xx xxxx  nCS0 address decoding  H' 00xx xxxx  Address to map on Avalon +H' PPPP 0000  Page Address  H' YYYY xxxx  Avalon Address + ARM add  nCS0 Avalon add Page

41. RB - EPFL/IC/LAP - A200841 FPGARM4U FPGA4U internal Avalon interface External Bus Interface 1 from ARM uC Integrates three External Memory Controllers:  Static Memory Controller  SDRAM Controller  ECC Controller Additional logic for NAND Flash Optional Full 32-bit External Data Bus Up to 23-bit Address Bus (up to 8 Mbytes linear) Up to 3 Chip Selects, Configurable Assignment:  Static Memory Controller on NCS0  SDRAM Controller or Static Memory Controller on NCS1  Static Memory Controller on NCS2, Optional NAND Flash support

42. RB - EPFL/IC/LAP - A200842 FPGARM4U FPGA4U internal Avalon interface Static Memory Controller (§8.2.2) of EBI1 8-, 16- or 32-bit Data Bus Multiple Access Modes supported : Byte Write or Byte Select Lines Asynchronous read in Page Mode supported (4- up to 32-byte page size) Multiple device adaptability : Control signals programmable setup, pulse and hold time for each Memory Bank (Compliant with LCD Module) Multiple Wait State Management : Programmable Wait State Generation External Wait Request (nWAIT signal) Programmable Data Float Time Slow Clock mode supported

43. RB - EPFL/IC/LAP - A200843 FPGARM4U FPGA4U internal Avalon interface  Addresses[22..0]  Data [15..0]  nCS0, nCS2  nOE  nWr[1..0]  nWAIT AT91SAM9263 EBI1

44. RB - EPFL/IC/LAP - A200844 EBI1 interface SRAM +SDRAM + NAND Flash

45. RB - EPFL/IC/LAP - A200845 EBI1 interface 1578 0 A : 4 GBytes Full memory space of the ARM9 nOE nWr0nWr1 8MB Max space for CS0 access 8MB nCS0 nCS2

46. RB - EPFL/IC/LAP - A200846 SMC documentation  SMC: Static Memory Controller  It's the mode to access the FPGA as a simple 16 bits wide memory  (Doc 6249.pdf, Atmel, Chap.22, p.197)  What are the timing access ?

47. RB - EPFL/IC/LAP - A200847 SMC documentation  Read Access  Programmable Timings : nRD_ SetUp Pulse (Hold) Cycle nCS_ Rd_SetUp Rd_Pulse (Rd_Hold)

48. RB - EPFL/IC/LAP - A200848 SMC documentation  Write Access  Programmable Timings : nWE_ SetUp Pulse (Hold) Cycle nCS_ Wr_SetUp Wr_Pulse (Wr_Hold)

49. RB - EPFL/IC/LAP - A200849 Wait cycles of EBI1/SMC  Internal wait clock cycles are provided by the way of the programmable set up, pulse and cycle (hold) times for read and write transfers cycles.  They are 2 modes for external Wait Cycles with this interface: Frozen mode Ready mode  The nWAIT signal is synchronized by 2 clocks rising edge before used inside the EBI  nWAIT can be asynchronous to Clk

50. RB - EPFL/IC/LAP - A200850 Wait cycles Frozen mode  At the sampling time of synchronized nWAIT, the internal clock counters stay with the same value until nWAIT is deactivated  Then they continue down counting to finish the transfer cycle

51. RB - EPFL/IC/LAP - A200851 Wait cycles Ready mode  The pulse time go to the programmed length, if synchronized nWAIT is active at this clk, Wait clk cycle are added until synchronized nWAIT is deactivated.

52. RB - EPFL/IC/LAP - A200852 nWAIT synchronization  For metastability filtering, the nWAIT signal is doubly synchronized before use in the Bus Interface. Thus it's effectiveness is only available 2 clock after it's activation !  Thus nWAIT doesn't need to be synchronized before entering the EBI.

53. RB - EPFL/IC/LAP - A200853 Wait cycles Latency  Set up and pulse lengths have to be programmed enough long for the nWAIT signal to be synchronized and accepted before the end of the pulse time.  minimal pulse length = nWAIT latency (from device selection) + 2 resynchronization cycles + 1 cycle p.220

54. RB - EPFL/IC/LAP - A200854 SMC Registers  Registers to initialize for EBI1 and SMC: EBI1_CSASRAM/SDRAM, PullUp, VddIO 0xFFFFED24 => 0xFFFFEC00 + 0x0124

55. RB - EPFL/IC/LAP - A200855 SMC Registers

56. RB - EPFL/IC/LAP - A200856 SMC Registers 4 CS_number configurations registers for each CS (p.228):  SMC_SetUp  SMC_Pulse  SMC_Cycle  SMC_Mode Hold = Cycle – Pulse - SetUp

57. RB - EPFL/IC/LAP - A200857 SMC Registers SMC_SetUp :Reset: 0x01 01 01 01  xxx_Setup * 128 + xxx_Setup :   0..31 - 128..159 clock cycles  CS0: 0xFFFFEA00  CS2: 0xFFFFEA20

58. RB - EPFL/IC/LAP - A200858 SMC Registers SMC_Pulse :Reset: 0x01 01 01 01  xxx_Pulse * 256 + xxx_Pulse :   1..63 - 256..319 clock cycles  CS0: 0xFFFFEA04 0: unpredictable  CS2: 0xFFFFEA24 result !!!!

59. RB - EPFL/IC/LAP - A200859 SMC Registers SMC_Cycle :Reset: 0x00 03 00 03  xxx_Cycle * 256 + xxx_Cycle :   1..127 - 256..383 – 512..639 – 768..895 clock cycles  CS0: 0xFFFFEA08 0: unpredictable  CS2: 0xFFFFEA28 result !!!!

60. RB - EPFL/IC/LAP - A200860 SMC Registers SMC_Mode :  PS: Page Size: 4, 8, 16, 32 By  PMEN: Page Mode Enable  TDF_Mode:DataFloatOptimization(1)  TDF_Cycles:DataFloatCycles, 0..15  CS0: 0xFFFFEA0C  CS2: 0xFFFFEA2C Reset: 0x10 00 10 00  DBW:DataBusWidth 8, 16, 32, -  BAT:Byte Access Type  ExnW_Mode:nWAIT Mode  Write_Mode:Ctrl by nWR(1)/nCS(0)  Read_Mode: Ctrl by nRD(1)/nCS(0)

61. RB - EPFL/IC/LAP - A200861 SMC Registers SMC_Mode :  BAT Byte Access Type 0: Write: nCS, nWE, nBS 0: Read: nCS, nRD, nBS 1: Write: nCS, nWR. 1: Read nCS, nRD  EXnW_ModeExternal Wait Mode 00Disabled 01Reserved 10Frozen 11Ready

62. RB - EPFL/IC/LAP - A200862 Memory Mapping 0x7000 0000 0x9000 0000

63. RB - EPFL/IC/LAP - A200863 Design of the Bridge  SMC access from ARM μC to FPGA  Master/Slave Avalon Bus  Needs to be initialized by NIOSII  Functions of the bridge can be programmed by ARM with nCS2 Access to memory mapping of 8MBytes to full 4 GBytes of Avalon Bus (in 32 bits mode) Mapping by a register and an adder.  FIFO for advanced features: Prefetch of next data in Read cycle End write cycle before real end of write cycle

64. RB - EPFL/IC/LAP - A200864 Design of the Bridge  As hypothesis: ARM clock : 200MHz FPGA clock: 50MHz Simple read/write cycle  To Do at least for bridge timings determination: Draw Read and Writes transfer cycles from EBI1 to Avalon Synchronize by double flip-flop in the bridge the : nCS - nOE for read nCS - nWr1 / nCS - nWr0 for write Determine the SetUp/Pulse/Cycle for read and write transfers for correct nWAIT generation (mode?)

65. RB - EPFL/IC/LAP - A2008 65 FPGARM4U Software design

66. RB - EPFL/IC/LAP - A200866 FPGARM4U ARM9 registers  The processor has 6 working spaces: System and User Fast interrupt (FIQ) Supervisor Abort Interrupt (IRQ) Undefined  Some registers are specific to the actual space

67. RB - EPFL/IC/LAP - A200867 FPGARM4U ARM9 registers  Some registers are allocated functions: Program Counter (PC, r15) Link Register (LR, r14), Stack Pointer (SP, r13) Current Processor State Register (CPSR)  SPSR are the Saved Processor State Register the CPSR is copied in the SPSR_xxx as mode change

68. RB - EPFL/IC/LAP - A200868 FPGARM4U ARM9 registers

69. RB - EPFL/IC/LAP - A200869 FPGARM4U ARM9 registers  In Thumb mode, less registers are available

70. RB - EPFL/IC/LAP - A200870 FPGARM4U ARM9 registers

71. RB - EPFL/IC/LAP - A200871 FPGARM4U ARM9 registers

72. RB - EPFL/IC/LAP - A200872 FPGARM4UBOOT  Start up of the ARM:  The processor start @ 0x00000000.  The internal ROM search for the serial memory  needs to be initialized  Connection as USB device and SAM-BA GUI from Atmel  Program the Serial Flash Memory with a Bootstrap program.

73. RB - EPFL/IC/LAP - A200873 FPGARM4U  The Bootstrap program initialize the processor and some interface  Search for OS to download: As USB Master, read a USB key  need to load a Kernel on the Key With Ethernet and NFS to load the kernel from a server

74. RB - EPFL/IC/LAP - A200874 FPGARM4U  Laboratory exercise: Install a Linux system on FPGARM4U Follows the instructions on: http://fpga4u.epfl.ch/wiki/FPGARM4ULinux You need a FPGARM4U board A USB Key A serial adapter