1. CMOS Layout poly diffusion side view top view metal cuts
CSE Autumn CMOS - 1

2. A View of Interconnect Layers
CSE Autumn CMOS - 2

3. Intel 4004 (1971)
CSE Autumn CMOS - 3

4. Pentium II (1996)
CSE Autumn CMOS - 4

5. Silicon in 2010 Die Area: 2.5x2.5 cm Voltage: 0.6 V
Technology: 0.07 m
CSE Autumn CMOS - 5

6. CMOS Inverter Layout
CSE Autumn CMOS - 6

7. Layout
4-input NAND gate
CSE Autumn CMOS - 7

8. Standard Cell Design Methodology
Example “stick diagram”
CSE Autumn CMOS - 8

9. Different Layouts are Possible
Different layouts for x =
CSE Autumn CMOS - 9

10. The Barrel Shifter
CSE Autumn CMOS - 10

11. 4x4 barrel shifter
CSE Autumn CMOS - 11

12. Logarithmic Shifter
CSE Autumn CMOS - 12

13. 0-7 bit Logarithmic Shifter3
Out3 A 2
Out2 A 1
Out1 A
Out0
CSE Autumn CMOS - 13

14. Latches
CSE Autumn CMOS - 14

15. Edge-Triggered Register (Master/Slave)
CSE Autumn CMOS - 15

16. Non-Overlapping Clocks
CSE Autumn CMOS - 16

17. Dynamic Register
CSE Autumn CMOS - 17

18. Registers and intervening logic
Switches and/or gates compute new values to store on next clock cycle
straightforward implementation CL 2 1
this circuit can use the entire clock cycle – no wasted time - a form of retiming CL CL 2 1
CSE Autumn CMOS - 18

19. Memory – Static Register Cells
8-transistor cell
bit
bit'
rd or wr
(rd or wr)'
sensing amplifier
rd/wr'
CSE Autumn CMOS - 19

20. Memory – Dynamic Register Cells
4-transistor cell
data-in
data-out' wr
dedicated busses for reading and writing rd
dynamic charge storage must be refreshed
CSE Autumn CMOS - 20

21. Memory – Dynamic Register Cells (cont'd)
3-transistor cell
pre-charge data-out' to generate 1 outputs
data-in
data-out' wr
no p-type transistors yield a very compact cell rd
CSE Autumn CMOS - 21

22. Memory – Dynamic Register Cells (cont'd)
1-transistor cell
precharge to intermediate voltage level
storage capacitor is one end of transistor
charge sharing with bus capacitance (Ccell << Cbus)
destructive read (must immediately write back)
extra demands on sense amplifier to detect small changes in bus charge
CSE Autumn CMOS - 22

23. Read-only Memory Cells
To store constants or other invariant data
Popular for control implementation
bit1
bit2
bit3
read1
read2
programmable logic array structure (exploits distributed NOR gate structure)
CSE Autumn CMOS - 23

24. Multi-ported Register Cells
Add more input and output transistors (similar for all variations)
Not usually done for 1-transistor cells
bus1
bus2'
row-bus1
row-bus2
bus2
bus1'
CSE Autumn CMOS - 24

25. Random access memory Decoding logic to select word
Attempt to make critical lines (data lines) as short as possible
Square aspect ratio rather than rectangular
2m k-bit words per row
2n by 2m*k bits
d e c o d e r n
memory cell array
2n rows
address of word (n+m bits) m
multiplexer ( 2m :1)
k bits wide (k bits/word)
CSE Autumn CMOS - 25

26. Decoders Decoder looks like AND-plane of ROM (all input combinations)
usually replicated throughout array
d e c o d e r
memory cell array n
rd/wr (row select)
CSE Autumn CMOS - 26
bit
bit'

27. Multiplexers Decode address into one-hot control signals
Each bit passes through single n-device or pass gate
note: bits of word in row are interleaved
word1
word2
word3
word4
bit1
bit2
from a decoder
CSE Autumn CMOS - 27

28. Content-Addressable Memory
Compares input to all entries in memory in parallel
applications: pattern recognition, TLBs, etc.
Require and encoder to indicate where a match occurred
perform inverse function of decoders
take a one-hot collection of signals and encodes them
e n c o d e r
content addressable memory cell array n
2n rows
m bits m
CSE Autumn CMOS - 28

29. Content-Addressable Memory Cells
Read and write like normal 6T memory cell
Match signal is precharged to 1, pulled to 0 if no match
send data on bit' and data' on bit for matching
match remains 1 if and only if all bits in word match
row select
match
bit
bit'
CSE Autumn CMOS - 29