1. Fabrication of CMOS Imagers
Vinay Keswani
Graduate Student
Imaging Science Department
02/19/04

2. Outline Introduction Impact on CMOS imagers Feature Size Impact of VDD
Substrate Doping
Oxide Thickness
Conclusion
References

3. Introduction
The first part of the idea of using “standard”CMOS technology for imagers is to use a widespread accessible process
With well-developed design tools
Standard design libraries
Fast turn-around time

4. Introduction
However, the question was naturally asked about how the rapid development of these“standard” processes would influence the imager performance.
Each aspect of scaling will be considered individually, along with the potential impact on CMOS imagers.

5. Feature Size
A new generation of CMOS devices is developed every three years, or less
Device dimensions are less than 0.7 times those of the previous generation
0.13 µm technology is in production
This is driven by the desire for
Lower power consumption
Higher speeds and Improved fill factor
Increased functionality and number of transistors

6. Feature size trend

7. Lower VDD Partly forced by reduced dimensions
Because electric fields cannot be too high (Electric Field = - VDD / X)
e.g. hot carrier effects & tunneling

8. Lower VDD » 1V

9. Impact on CMOS imagers Reduced analog voltage swing, VDD – VT
Reduced dynamic range
Analog signal processing becomes difficult

10. Substrate Doping
Xj (Junction Depth) - Source,Drain are dependent on the substrate doping of the wafer (Xj ~ 1/ Nsub)
Substrate doping is increasing over the years in order to minimize short-channel effects
e.g. Punchthrough

11. Substrate Doping

12. Impact on CMOS imagers
Due to associated reduction in minority carrier diffusion length, Ln
Good – reduces crosstalk between pixels
Bad – reduces effective volume for photo-charge collection.

13. Oxide Thickness
As the supply voltage decreases, so too must the threshold voltage
Although this is also affected by substrate doping
VT is dependent on 1/Cox, and therefore tox must be reduced, since Cox = eSi/tox

14. Oxide Thickness

15. Impact on CMOS imagers
Reduced voltage swing, as before, since VDD scales
Gate tunneling current potentially important for some MOS capacitor devices

16. Conclusion In the end, the balance depends on the application
It is likely that a continuum of techniques will develop between pure CCD and pure CMOS or the combination of both….

17. References Silicon VLSI Technology by Plummer
P. Lee et al. (1995), “An active pixel sensor fabricated using CMOS/CCD process technology”, 1995 IEEE Workshop on CCDs and Advanced Image Sensors, Dana Point, CA

18. Acknowledgements
Thank you very much to Prof. Rolando for his support and help !!!

19. Questions