1. 경종민 kyung@ee.kaist.ac.kr 1 Future Prospect of IC Technology (ITRS)-II 2002. 9.11

2. 2 DT Methodology Precepts Design Methodology combines 1)enforcement of system specifications and constraints via top-down planning and search (system specification and constraints) with 2)bottom-up propagation of constraints due to physical laws, limits of manufacturing technology and system cost limits)

3. 3 DT Methodology Precepts Future Design Methodologies and component tools –Exploit reuse –Evolve rapidly( evolution of suite vectors from simulation to verification, constraints for synthesis and optimization, and test) –Avoid iteration –Replace verification by prevention(ex; lower-level problems, i.e., crosstalk/delay uncertainty, can be better addressed by upper-level prevention, i.e., shielding/repeater insertion)

4. 4 DT Methodology Precepts Future Design Methodologies and component tools –Improve predictability –Orthogonalize concerns; divide and conquer, treat separately if possible(computing and communication, behavior and architecture, etc.) –Expand scope; gather and conquer, treat together if possible(digital and analog, digital HW and software, internal,, operation and human interface, multi-level modelling, simulation) –Unify; synthesis and analysis, logical/physical/timing, design and test.

5. 5 DT Methodology Methodology Precepts

6. 6 Design Technology DT Area –Design Process –System-Level Design –Logical, Circuit, and Physical Design –Design Verification –Design Test With five motifs(cross-cutting challenges); –Productivity –Power –Manufacturing integration –Interference –Error tolerance

7. 7 Design Technology

8. 8 DT Crosscutting Challenges Productivity Power Manufacturing Integration Interference Error-Tolerance

9. 9 DT Motif (Productivity) Verification bottleneck Reliable and predictable silicon implementation fabrics with high-level design handoff Embedded software design crisis Design team/process management system Automation of AMS(analog/mixed signal) synthesis, verification and test Time-to-market reduction via standards and platforms for interoperability

10. 10 DT Motif (Power) Power management gap; For constant power dissipation(0.1W) for hand- held device chips, memory(logic) occupies 70%(30%) in 2004, 82%(18%) in 2010, and 96%(4%) in 2016. Trade-off between increasing power density (performance loss and instability due to thermal impact) and supply voltage reduction (slow switching and noise sensitivity) Power optimization with multi- Vt, multi-Tox, multi-Vdd

11. 11 DT Motif (Manufacturing integration) Test interface; new fault models(i.e., crosstalk and path delay) along with BIST and ATPG can help solve cost and speed problems of tester. Die-package-board co-optimization Manufacturing variability-aware circuit design, design for regularity(ex; precision capacitor as a cocentric, symmetric array of unit capacitors) Manufacturing NRE cost reduction thru smart interface to mask production and inspection

12. 12 DT Motif (Interference) Problem sources; noise and interference due to increasingly largely number of capacitively and inductively coupled wires, supply voltage IR drop and ground bounce, thermal impact on off-current and wire R, substrate couplings. Methodologies; repeater insertion rules for long interconnects, slew rate control rules, P/G distribution rules for inductance management

13. 13 DT Motif (Error Tolerance) Automatic introduction of redundant logic and on-chip reconfigurability for fault tplerance Development of adaptive and self-repairing circuits Software-based fault tolerance

14. 14 Design Process Challenges Near-term challenge [ ≥65nm / Through 2007 ] 1.Design Sharing and Reuse –Geographically distributed and multi-company design projects –Integration of multi-vendor and internal design technology (MPU, SOC) –Standard information model for IC design data, with standard interface (access mechanism) adopted across tools, database (MPU, SOC) –Tool interoperability that minimized data translation time and redundancy to reduce design cycle times (MPU, SOC) –Reduction of integration cost

15. 15 Design Process Challenges 2.Increased System and Silicon Complexities –Device count, scaling, operating frequency, power and noise management (MPU, SOC) –Incremental analysis and optimization capability for constraint-dominated design, with runtimes proportional to amount of design changed (MPU, SOC) –Scalable design optimization algorithms –Concurrent execution of design and analysis tools with appropriate objectives and abstractions (MPU, SOC) –Common device, wafer recipe and equipment characterizations, controlled by process owner and packaged for “ immutable interpretation ” by design and analysis tools

16. 16 Design Process Challenges 3.Time-to-market for cost-driven SOC –Common information models to support reuse and (cost- driven) design space exploration (SOC) –Design rules and information models (e.g., abstracts) that assure reusability; design and validation tools to assure these rules for reusable design IP (SOC) –DT integration for hardware/software, digital/analog, MEMS, memory, design tools (AMS, SOC) –Synthesis of analog designs comparable to digital RTL- based synthesis (AMS, SOC) 4.Systematic improvement of design process and design productivity –Standard design process metrics, calibration and benchmarking

17. 17 Design Process Challenges Long-term challenge [ ≤65nm / Beyond 2007 ] 1.Time-to-market for cost-driven SOC –Platform- and application- (and even design-) specific design flows via reusable, interoperable tools (SOC) –Synthesis of mixed-technology design (including analog) comparable to digital RTL-base synthesis (AMS, SOC) –System cost minimization tools spanning from standardized process description to supply chain management (SOC) –Higher-level verification of function, performance and manufacturability (SOC, MPU)

18. 18 Design Process Challenges 2.Systematic improvement of design process and design productivity –Design technology productivity analysis and optimization tools –Predictable physical implementation flows, along with predictive models for such flows

19. 19 System-Level Design –Enable to allocate and exploit silicon resources in a top-down and structured fashion –Design freedom either behavior for system function, or architecture for system platform with two architecture components, (HW,SW). –SL DT has both methodological aspect (space exploration and model refinement) and design automation aspect(tools and algorithms) –Rely on extensive reuse of predesigned IP blocks and functions –Major SL DT trends: 1)reuse and platform-based design 2)increasingly prohibitive cost of communication/synchronization 3)heterogeneous integration 4)embedded software

20. 20 SL Design Challenges [ ≥65nm / Through 2007 ] 1.System Complexity –Higher-level abstraction and specification Design language infrastructure for complex models C++ derivatives such as SystemC and others –Dynamism and softness Enable the system to adapt at runtime under the influence of use requirements Enables a system to be modified or reprogrammed New abstractions are required for such runtime modification of function and architecture –System-level reuse Already some progress in RT- and Layout-level design reuse No methodology and associated design tool Reuse of complex HW-SW architectures via methods –Such as platform-based design

21. 21 SL Design Challenges 1.System Complexity (continued) –Design space exploration and system-level estimation For optimization of the function-architecture mapping –Power, area throughput, etc –Efficient behavioral synthesis and SW compilation Automated mappings from function to architecture –Behavioral synthesis for hardware and compilation of software –Automatic interface synthesis Synthesizing Interfaces (between HW-HW, HW-SW, SW-SW) Instead of hand-designed or drawn from parameterized libraries

22. 22 SL Design Challenges 2.System Power Consumption –Energy-performance-flexibility tradeoffs –Novel data transfer and storage techniques 3.Integration of heterogeneous technologies –Codesign Partitioning and codesign HW-SW, analog-digital, fixed-reprogrammable, die-package-board –Analog behavioral modeling and synthesis: Non-scalability Automated analog circuit synthesis and optimization Language-level modeling methodologies –Top-down implementation planning with diverse fabrics Single hierarchical mixed-technology planning environment

23. 23 SL Design Challenges 4.Embedded Software –SW-SW codesign into highly programmable platform –System capture and abstraction System functional model, communication model –New automation from high level description to HW-SW implementations, include SW synthesis –HW-SW coverification 5.Links to verification, test and culture Shifting design focus from block creation to block reuse –Integration-oriented verification and test architecture –Divergent design practices and culture Supporting connection point, links between system-level design and implementation –Between ever-greater abstractions and detailed physical manufacturing realities

24. 24 SL Design Challenges [ ≤65nm / Beyond 2007 ] 1.System Complexity –Communication-centric design and network-based communication on chip –Design robustness 2.System Power Consumption –Non-scaling of centrally organized architectures –Building large systems from heterogeneous SOCs 3.Integration of heterogeneous technologies –Total system integration including new integrated technologies (e.g., MEMS, electro-optical, electro-chemical, electro-biological or organic)

25. 25 Logical, circuit, Physical Design [ ≥65nm / Through 2007 ] 1.Efficient and Predictable Implementation –Scalable, incremental analyses and optimization –Unified implementation/interconnect planning and estimation/prediction –Synchronization and global signaling –Heterogeneous system composition –Links to verification and test 2.Variability and design-manufacturing interface –Uncertainty of fundamental chip parameters (timing, skew, matching) due to manufacturing and dynamic variability sources (MPU, SOC, AMS) –Process modeling and characterization –Cost-effective circuit, layout and reticle enhancement to manage manufacturing variability

26. 26 Logical, circuit, Physical Design 3.Silicon complexity, non-ideal device scaling and power management –Leakage and power management –Reliability and fault tolerance –Analysis complexity and consistent analysis / synthesis objective 4.Circuit design to fully exploit device technology innovation –Support for new circuit families that address power and performance challenges –Implementation tools for SOI –Analog synthesis

27. 27 Logical, circuit, Physical Design [ ≤65nm / Beyond 2007 ] 1.Efficient and Predictable Implementation –Reliable, predictable fabric- and application-specification implementation platforms –Cost-driven implementation flows 2.Variability and design-manufacturing interface –Increasing atomic-scale variability effects 3.Silicon complexity, non-ideal device scaling and power management –Recapture of reliability lost in manufacturing test 4.Circuit design to fully exploit device technology innovation –Increasing atomic-scale effects –Adaptive and self-repairing circuits –Low-power sensing and sensor interface circuits; micro-optical devices

28. 28 Design Verification Major role to the design process –The dominant cost in the design process –Verification engineers outnumber designers (2~3times) in the most complex designs Why –Increasing functional complexity –Other aspects of the design process has produced enormous progress, leaving verification as the bottleneck Current Verification Method –Trial-and-error verification method Verify the functionality by repeatedly building models Simulating them on ad hoc selection of vectors –Slow and unscalable Doubly-exponential growth in functional complexity

29. 29 Design Verification Challenges [ ≥65nm / Through 2007 ] 1.Increase Verification Capacity To provide high quality verification coverage for large, complex design –Verification exponential in design size –Need high coverage –Need to handle large designs –Semi-formal techniques

30. 30 Design Verification Challenges 2.Robustness verification tools Verification algorithms highly unpredictable and depend on highly temperamental heuristics –Improved heuristics for the verification algorithms –Improved characterization of the difficult of verifying a given design 3.Verification metrics Quantify the quality of a verification effort (a meaningful notion of coverage) –Behavior coverage –Realistic bug model –Algorithms to determine bug coverage

31. 31 Design Verification Challenges 4.Software verification –Software intrinsically more difficult to verify Much of the functionality of SOCs will be defined by software SW and SW-HW verification is a major SOC verification challenge –Traditional software verification techniques inapplicable Hard to verify, due to more complex, dynamic data and enormous state space Too labor-intensive to be applicable for SOC –Verification Integrated hardware/software system –Robust verification methods for software –Design-for-verifiability

32. 32 Design Verification Challenges 5.Verification Reuse Verification Methodology for Rapid verification of a system assembled from pre-designed (pre- verified) block Near-term: standardized IP interconnects (on-chip buses) –Must allow reuse of verification of IP blocks –Specify abstract behavior of IP blocks –Specify environmental constraints of IP blocks –Hierarchical verification algorithms

33. 33 Design Verification Challenges 6.Specialized verification methodology –MPU Different cost-benefit trade-off Need exceptionally high capacity Must be very predictable due to –Design cycle is very long –Multiple design teams are pipelined 7.Specialized design-for-verifiability –Domain-specific design-for-verifiability techniques Self-checking-process, watch-dog processor –Effective in reducing verification cost While imposing minimal area and performance penalties 8.New kinds of concurrency –Verification techniques to handle the new forms of concurrency Cache coherence, chip-level multiprocessing, simultaneous multithreading

34. 34 Design Verification Challenges [ ≤65nm / Beyond 2007 ] 1.Design for verifiability –New methodology needed Understandings of how design errors occur  producing easy-to- verify design Sequential testability (scan-based testing) –Characterize and minimize performance and area impact 2.Higher levels of abstraction –New algorithm needed –Verification methods for the higher-levels of abstraction As design moves to a level of abstraction above RTL –Complexity of design enabled by higher-level design –Equivalence checking between the higher-level and lower-level models

35. 35 Design Verification Challenges 3.Human factors in specification –Specifications of correctness will become unmanageable –Need to understand what kinds of specifications are most understandable –Need to consider how to make specifications modular and modifiable 4.Verification of non-digital systems –Hybrid systems verification for analog effects –Hybrid systems verification for analog properties –Verification of probabilistic systems 5.Heterogeneous systems –How to model, analyze, and verify MEMS, EO devices, and electro-biological device

36. 36 Design Test High speed device interface –Faster I/O Speed: multiple GHz –Complex I/O protocol: source synchronous, differential, simultaneous bidirection, differential voltage swings Highly integrated SOC design –Larger integrated devices Non-linear complexity growth for design tools, DFT, manufacturing test –Integration of analog, mixed signal Nonlinear increase in the cost of testability, design verification, manufacturing test

37. 37 Design Test Challenges [ ≥65nm / Through 2007 ] 1.At-speed test with increasing frequencies –Continuation of at-speed functional test with increased clock frequencies –At-speed structure test with increased clock frequencies –Test and on-chip measurement techniques for multi-GHz serial ports 2.Capacity gap between DFT/Test generation/Fault grading tools and design complexity –Better EDA tools for advanced fault models –DFT to enable low-cost ATE –Non-intrusive logic BIST –AMS DFT/BIST, especially at beyond-baseband frequencies 3.Quality and yield impact due to test equipment limits –Power and thermal management during test –Fault diagnosis and design for diagnosability –Yield improvement and failure analysis tools and methods

38. 38 Design Test Challenges 4.Signal integrity testability and new fault models –Signal integrity testability –Fault modes for analog failures 5.SOC test –Integration of SOC test methods onto test equipment platform –Integration of multiple fabric-specific test methodologies –DFT, BIST and test methods compatible with core-based SOC environment and constraints –Embedded memory built-in self-diagnosis and self-repair –Test reuse

39. 39 Design Test Challenges [ ≥65nm / Through 2007 ] 1.Integrated self-testing for heterogeneous SOCs –Test of multi-GHz RF front end on chip –Use of on-chip programmable resources for SOC self-test –Dependence on self-test solution for SOC –(Analog) signal integrity test issues caused by interference from digital to analog circuitry –Test methods for heterogeneous SOC including MEMS and EO components

40. 40 Design Test Challenges 2.Diagnosis and reliability screens –Diagnosis and failure analysis for AMS parts –Design for efficient and effective burn-in to screen out latent defects –Quality and yield impact due to test equipment limits –New timing-related fault modes for defects/nose in nanometer technologies 3.Fault tolerance and on-line testing –DFT and fault tolerant design for logic soft errors –Logic self-repair using on-chip reconfigurability –System-level on-line testing