1. Somervill RSC 1 125/MAPLD'05 Reconfigurable Processing Module (RPM) Kevin Somervill 1 (kevin.m.somervill@nasa.gov) Dr. Robert Hodson 1 (robert.f.hodson@nasa.gov) Dr. John Williams 2 (jwilliams@itee.uq.edu.au) Dr. Robert Jones 3 (robert.jones@akspace.com) 1 NASA Langley Research Center 2 The University of Queensland, Australia 3 ASRC Aerospace Corp.

2. RSC Somervill 2 125/MAPLD'05 Presentation Topics RSC Platform Architectural Overview RPM Architecture Block Diagram Interface FPGA Block Diagram RPM Physical Implementation Mitigation Methods System Modeling and Software Development Challenges and Issues

3. RSC Somervill 3 125/MAPLD'05 RSC Platform Architectural Overview Collection of one or more modular stacks of computing elements RPM is core reconfigurable component hosting reconfigurable FPGA fabric

4. RSC Somervill 4 125/MAPLD'05 RPM Architecture Block Diagram

5. RSC Somervill 5 125/MAPLD'05 Interface FPGA Block Diagram Alternatives and issues –Crossbar logic – potential enhancement to first pass architecture if greater bandwidth is required –RapidIO – an attractive possibility, but considered to be too costly and complex for most applications. –Hypertransport – Similar to RapidIO, it was considered to be excessively more than needed.

6. RSC Somervill 6 125/MAPLD'05 RPM Physical Implementation Form factor –14cm x 9.59cm Components –Actel AX2000 (CCGA624) –Xilinx 4VFX60 (CF1144) –3D-Plus Stacked SDRAM (512MB) –Flash (8MB at least) –Texas Instrument TLK2711 MGT –Voltage Regulation (Note: Prototype will use XC2V3000 instead of the AX2000) High Speed Serial Interface Application FPGA (V4FX60) PCI-104 Connector PCI-104 Extension Interface FPGA (AX2000) Voltage Regulation Memory Subsystem External I/O

7. RSC Somervill 7 125/MAPLD'05 Mitigation Methods TMR –In the Xilinx with XTMR tool and the Actel is TMR at the die. Including I/O pins (3x for Unidirectional – 6x for Bidirectional!!) Data “Scrubbing” –Configuration data for Xilinx FPGA –SDRAM data Fast Double Error Correction Triple Error Detection –Pipelined error correction engine for 32-bit data/16-bit check field –Single Error Correction Double Error Detection is the fall back Shielding for the stacks with overlapping carriers. Radiation Tolerant components (target of 100krad) Thorough Design Methodologies and popular development tools…

8. RSC Somervill 8 125/MAPLD'05 Systems Modeling and Software Development with formal modeling –Petri nets models provide performability models Performability considers both reliability and performance aspects in a unified model. –Petri nets provide a mathematically based rigorous approach to system evaluation and development Petri nets converted to SystemC models –Serve as faster lower level system simulation models –SystemC model provides simplified path to software evaluation for prospective applications. Operating System Support with uCLinux TM –Standard development environment (GNU toolchain) –MPI (sort of)

9. RSC Somervill 9 125/MAPLD'05 Development Challenges and Issues TMR of the reconfigurable logic (especially the Microblaze soft core processor) Caching architecture across the SLiP interface. –Development of a low latency, tiered cache structure for embedded soft processors. Fabrication with fine pitch CGA components (4VFX60) –May require microvias and blind vias Availability of various technologies –Non-volatile memory (FLASH and EEPROM) –Small form factor, high-efficiency DC voltage regulators

10. Somervill RSC 10 125/MAPLD'05 Back Up Slides

11. RSC Somervill 11 125/MAPLD'05 Design Status as of 8/1/2005 Currently still working some architectural formulation, but the base structure is completed. –Reconfigurable nature of the prototype enables architecture trades post hardware development. Schematics complete and layout proceeding. Hardware prototypes expected at the end of the fiscal year.

12. RSC Somervill 12 125/MAPLD'05 Example Soft Processor Application

13. RSC Somervill 13 125/MAPLD'05 Example Custom Hardware Application