1. 32-bit Pipelined RISC Processor Group 1 aka “Go Us” Alice Wang Ann Ho Jason Fong CS m152b TA: Young Cho Lab section 1

2. General Review of a Pipelined Processor Instruction Memory Register File ALU Data Memory PC Control IF/ID ID/EXEX/MEMMEM/WB

3. Memory Controller Design Design challenge: 32-bit processor with 16-bit memory interface On every memory access, need to get two words from memory Solution: Clock memory controller twice as fast as rest of processor Results in a memory access on the rising and falling edge of the processor’s clock cycle Data Memory One request16-bit interface Two 16-bit words 32-bit word ? Request Processor Memory 16-bits 32-bits 32-bit

4. Instruction Format R-type instruction 4 bits remaining 28 bits vary according to instruction type General instruction format 31 28 opcode 27 25 rs 24 22 rt 21 19 rd unused 3 0 funct 3 0 funct I-type instruction 31 28 opcode 27 25 rs 24 22 rt unused 15 0 imm16 31 28 opcode 27 25 rs 24 22 rt unused 15 0 imm16 J-type instruction 31 28 opcode unused 15 0 imm16 31 28 opcode 27 25 rs 24 22 rt 21 19 rd 31 28 opcode unused 15 0 imm16

5. R-type instructionsI-type instructionsJ-type instructions

6. ALU with Multiplier Our_mult

7. 0 0 0 0 0 0 0 0 0 Multiplier Uses a series of shifts and additions Example: 13 x 11 = 01101 x 01011 01101 01011 multiplicand multiplier 01101 x 1 = 01101 HI LO +0 1 1 0 = 1 = 01101+ 0 0 1 1 1 0 11  0 0 1 0 0 0 1 1 1 1 = 143

8. multiplier (more efficient, but more hardware)

9. Data Forwarding ID/EXEX/MEMMEM/WB Forward From ALU output Forward From memory output

10. Hardware NOP Insertion NOP 1 IF/ID PC Adder Hold PC value Insert NOP

11. Data Forwarding and Stall Insertions: Observed Results Sample program: Bubble-sort 6 numbers Assembler insertion of NOPs Machine code size: 66 words of memory Execution time: ~750 clock cycles Hardware data forwarding and NOP insertion: Machine code size: 35 words of memory Execution time: ~400 clock cycles

12. Data Forwarding and Stall Insertions: Observed Results Benefits: Savings in memory and execution time Much simpler assembler Drawbacks: Hardware is now more complex Tradeoff between hardware complexity and software complexity Also demonstrates benefits of understanding the underlying architecture when designing an assembler

13. Conclusion Some problems we encountered: Off by one stage in pipeline Lack of experience with VHDL Order of bits from memory In Conclusion... Knowledge from previous courses Further research Simple RISC processor Pipelining Multiplier Data Forwarding and Hardware NOP’s

14. References Hennessey and Patterson, Computer Organization and Design (2nd Ed.), 1998, pages 476-495 Donaldson, John L., “Pipeline Hazards”, http://occs.cs.oberlin.edu/faculty/jdonalds/317/lecture08.html Ercegovac, Intro To Digital Systems Institute of Electronics, Information and Communication Engineers. "High Speed and Very Compact Two's Complement Serial/Parallel Multipliers Using Xilinx's FPGA"., Abdelkrim Kamel Oudjida 19 Nov. 2002, http://search.ieice.org/2001/pdf/e84-a_5_1339.pdf

15. Applause Please Thank You