1. 1 Lecture 9 Demultiplexers Programmable Logic Devices  Programmable logic array (PLA)  Programmable array logic (PAL)

2. 2 Switching networks logic blocks Multiplexer (MUX)  Routes one of many inputs to a single output  Also called a selector Demultiplexer (DEMUX)  Routes a single input to one of many outputs  Also called a decoder control

3. 3 Logic sharing example 4:1 MUX A 0 A 1 A 2 A 3 C 0 C 1 C 2 C 3 B 0 B 1 B 2 B 3 Complex Logic ABC D 2:4 DEMUX S1S1 S0S0 D 0 D 1 D 2 D 3 Computes the output value selected by the control inputs

4. 4 Demultiplexers Basic concept  Single data input; n control inputs (“selects”); 2 n outputs  Single input connects to one of 2 n outputs  “Selects” decide which output is connected to the input

5. 5 Demultiplexers The input is called an “enable” (G) 1:2 Decoder: Out0 = G  S' Out1 = G  S 2:4 Decoder: Out0 = G  S1'  S0' Out1 = G  S1'  S0 Out2 = G  S1  S0' Out3 = G  S1  S0 3:8 Decoder: Out0 = G  S2'  S1'  S0' Out1 = G  S2'  S1'  S0 Out2 = G  S2'  S1  S0' Out3 = G  S2'  S1  S0 Out4 = G  S2  S1'  S0' Out5 = G  S2  S1'  S0 Out6 = G  S2  S1  S0' Out7 = G  S2  S1  S0 C AB 0123456701234567 S2 3:8 Demux S1S0 G

6. 6 Demultiplexers: Implemtation Out 0 G S Out 1 2:4 demux 1:2 demux

7. 7 Demultiplexer as logic block A n:2 n demux can implement any function of n variables  Use variables as select inputs  Tie enable input to logic 1  Sum the appropriate minterms (extra OR gate) demultiplexer “decodes” appropriate minterms from the control signals C AB 0A'B'C' 1A'B'C 2A'BC' 3A'BC 4AB'C' 5AB'C 6ABC' 7ABC S2 3:8 Demux S1S0 1

8. 8 Demultiplexer as logic block F1 = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A'+B'+C'+D') AB 0A'B'C'D' 1A'B'C'D 2A'B'CD' 3A'B'CD 4A'BC'D' 5A'BC'D 6A'BCD' 7A'BCD 8AB'C'D' 9AB'C'D 10AB'CD' 11AB'CD 12ABC'D' 13ABC'D 14ABCD' 15ABCD 4:16 Demux Enable = 1 CD F1 F2 F3

9. 9 Cascading demultiplexers 5:32 demux

10. 10 Programmable logic Concept: Large array of uncommitted AND/OR gates (actually NAND/NOR gates)  You program the array by making or breaking connections Programmable block for sum-of-products logic inputs outputs product terms AND array OR array

11. 11 All two-level functions available You "program" the wire connections This is a 3-input, 5-term, 4-function programmable logic array (PLA). Connections ("fuse") are designed to break down under high current. After analyzing Boolean equations, software determines which fuses should be blown.

12. 12 Example F0 = A + B'C' F1 = AC' + AB F2 = B'C' + AB F3 = B'C + A

13. 13 Short-hand notation Draw multiple wires as a single wire or bus × signifies a connection After Programming ABCD Before Programming F0 = AB + A'B' F1 = CD' + C'D

14. 14 PLA example F1 = ABC F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C Think of as a memory-address decoder Memory bits 0 1 0 0 1 0 1 1 ABCF1F2F3F4F5 000 0 0 1 1 0 001 0 1 0 1 1 010 0 1 0 1 1 011 0 1 0 1 0 100 0 1 0 1 1 101 0 1 0 1 0 110 0 1 0 1 0 111 1 1 0 0 1

15. 15 PLAs versus PALs We've been looking at PLAs  Fully programmable AND/OR arrays Programmable array logic (PAL)  Programmable AND array  OR array is prewired Cheaper and faster than PLAs

16. 16 Example: BCD to Gray code ABCDWXYZ000000000001000100100011001100100100011001011110011010100111101110001001100110001010XXXX1011XXXX1100XXXX1101XXXX1110XXXX1111XXXXABCDWXYZ000000000001000100100011001100100100011001011110011010100111101110001001100110001010XXXX1011XXXX1100XXXX1101XXXX1110XXXX1111XXXX 0000X1 0101X1 1101XX 1001XX 0001X0 0101X0 1100XX 1000XX 0000X1 0110X0 1101XX 1010XX A D AB CD 00011110 C B K-map for W A D AB CD 00011110 C B A D 0001X0 0101X0 1111XX 1011XX AB CD 00011110 C B A D AB CD 00011110 C B K-map for X K-map for YK-map for Z

17. 17 Wiring a PLA Minimized functions: W = A + BC + BD X = BC' Y = B + C Z = A'B'C'D + BCD + AD' + B'CD'

18. 18 Wiring a PAL Minimized functions: W = A + BC + BD X = BC' Y = B + C Z = A'B'C'D + BCD + AD' + B'CD' Fine example for the use of PAL (because no shared AND terms) Many AND gates wasted, but still faster and cheaper than PLA

19. 19 Implementation comparison PLA: No shared logic terms in this example 10 decoded functions (10 AND gates) PAL: Z requires 4 product terms Need a PAL that handles 4 product terms for each output 16 decoded functions (16 AND gates) 6 unused AND gates Example is a good candidate for PALs:  10 of 16 possible inputs are decoded  No sharing among AND terms