1. Notices You have 18 more days to complete your final project!
Collaborate with each other (NOT Copy!!)
Presentations will be held on March 7 (Tuesday) and March 9 (Thursday) In Rm. 301 During Lab Hours
Magiboard, Projector, Notebook PC will be available to you
Use the Color Printer!

2. COMBINATIONAL LOGIC Complete Reading 4.2 Start Reading 4.3
(dynamic CMOS)
Combinational Logic

3. Fast Complex Gate - Design Techniques
Transistor Sizing
Minimize tp(worst-case)
Progressive Sizing
As long as fan-out capacitance dominates
Transistor Ordering
Minimize Critical Path
Improved Logic Design
Minimize fan-in
Lumping all the internal capacitances of the circuit into one load capacitor (CL) is an oversimplification. If the individual capacitors at the internal nodes are considered separately, it can be seen that transistor M1 has to supply discharging current to all the capacitors, but MN must only discharge CL. Hence MN can be smaller than M1. The transistors can be sized progressively as shown. Example 4.3 in the text shows how progressive sizing can yield a speed improvement of 30% over a non-sized approach.
Note: Only the PDN is considered here. The same approach applies to the PUN.

4. Fast Complex Gate - Design Techniques
Buffering
Isolate fan-in from fan-out
Ratioed Logic (NMOS, Pseudo-NMOS)
To reduce the # transistors
Adaptive Load
Reduce power dissipation during standby
Lumping all the internal capacitances of the circuit into one load capacitor (CL) is an oversimplification. If the individual capacitors at the internal nodes are considered separately, it can be seen that transistor M1 has to supply discharging current to all the capacitors, but MN must only discharge CL. Hence MN can be smaller than M1. The transistors can be sized progressively as shown. Example 4.3 in the text shows how progressive sizing can yield a speed improvement of 30% over a non-sized approach.
Note: Only the PDN is considered here. The same approach applies to the PUN.

5. Fast Complex Gate - Design Techniques
Dual Cascode Voltage Switch Logic (DCVSL)
No static power dissipation!
More complex (=> more area)
Pass Transistor Logic
N transistors
No Static power consumption
Lumping all the internal capacitances of the circuit into one load capacitor (CL) is an oversimplification. If the individual capacitors at the internal nodes are considered separately, it can be seen that transistor M1 has to supply discharging current to all the capacitors, but MN must only discharge CL. Hence MN can be smaller than M1. The transistors can be sized progressively as shown. Example 4.3 in the text shows how progressive sizing can yield a speed improvement of 30% over a non-sized approach.
Note: Only the PDN is considered here. The same approach applies to the PUN.

6. Pass-Transistor Logicu t s
Switch
Network
Out A B

7. NMOS-only switch does not pull up to 5V, but 5V - V
A =
5 V B
C = 5 V C L M 2 1 n
Threshold voltage loss causes
static power consumption
does not pull up to 5V, but 5V - V TN

8. Solution 1: Transmission GateB C

9. Resistance of Transmission Gate

10. Pass-Transistor Based Multiplexer
VDD
GND
In1 S S
In2

11. Transmission Gate XOR A B F M1 M2
M3/M4

12. Delay in Transmission Gate Networks

13. Elmore Delay (Chapter 8)1 C 2
i-1 i -1 N V in
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin, then delay at node N is t
C = j
j i = å
i 1
j 1
See page 475

14. Delay Optimization

15. NMOS Only Logic: Level Restoring TransistorDD V
Level Restorer DD M r B M 2 X A M n
Out M 1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS

16. Level Restoring Transistor
(a) Output node
(b) Intermediate node X 2 4 6 t
(nsec)
-1.0
1.0
3.0
5.0 V o u ( ) X
with
without B

17. Solution 3: Single Transistor Pass Gate with VT=0
Out V DD 5V 0V
WATCH OUT FOR LEAKAGE CURRENTS

18. Complimentary Pass Transistor Logic

19. 4 Input NAND in CPL

20. Standard Cell Layout Methodology
Appendix C
Page 264
Combinational Logic

21. Standard Cell Layout Methodology

22. Two Versions of (a+b).c a c b x GND V (a) Input order { a c b }DD
(a) Input order {
a c b }
(b) Input order {
a b c

23. Logic Graph
Euler Path

24. Consistent Euler Path
GND x V DD c b a i j
{ a b c}

25. Example: x = ab+cd

26. Combinational Logic: Dynamic CMOS
Read Section 4.3
Combinational Logic

27. Dynamic Logic • Precharge 2 phase operation: • Evaluation V f M Out CDD
PDN f In 1 2 3
Out
PUN C L
network n
2 phase operation:
• Evaluation
• Precharge

28. Example M V f Out A B C • N + 1 Transistors • RatiolessDD f
Out A B C
• N + 1 Transistors
• Ratioless
• No Static Power Consumption
• Noise Margins small (NM L )
• Requires Clock

29. Transient Response 0.00e+00 2.00e-09 4.00e-09 6.00e-09 t (nsec) 0.0V o u t ( l ) f
out
PRECHARGE
EVALUATION

30. Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4 f
GND