1. Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional Teknik Komputer Universitas Gunadarma

2. Tri-state buffers XOR & XNOR DecodersEncodersMultiplexersDemultiplexers Topic #6 – Combinational Logic Building Blocks

3. Outputs: 0, 1, or Hi-Z (high impedance) Tri/Three-state buffers Hi-Z  Don’t care CMOS transmission gate A B EN A·EN’+B·EN Can tie multiple outputs together  one at a time is driven

4. 2-input XOR gates True if and only if the two inputs are different XNOR: complement of XOR May be used as comparator

5. XOR and XNOR symbols Why are they equivalent?

6. Gate-level XOR circuits Can we make it using only NAND gates?

7. CMOS XOR with transmission gates IF B==1 THEN Z = !A; ELSE Z = A;

8. Multi-input XOR? What is X  Y  Z = ? X’ · Y · Z + X · Y’ · Z + X · Y · Z’ + X’ · Y’ · Z’ TRUE if odd number of inputs are TRUE Associativity for XOR, just like AND & OR? Parity computation – to detect single bit error

9. Parity tree Faster with balanced tree structure

10. Convert m-bit coded inputs into n-bit outputs Typically m<n Typically m<n E.g., n-to-2 n, BCD decoders E.g., n-to-2 n, BCD decoders Enable: prevent changes in output due to undesired changes in input Decoders

11. 4-bit input indicates the number to display, and thus control the on/off of the 7 segments. Recall K-map minimization with Don’t cares … EN D C B Aa b c d e f g 0 x x x x0 0 0 0 0 0 0 1 0 0 0 01 1 1 1 1 1 0 1 0 0 0 10 1 1 0 0 0 0 1 0 0 1 01 1 0 1 1 0 1 1 0 0 1 11 1 1 1 0 0 1 1 0 1 0 00 1 1 0 0 1 1 1 0 1 0 11 0 1 1 0 1 1 1 0 1 1 00 0 1 1 1 1 1 1 0 1 1 11 1 1 0 0 0 0 1 1 0 0 01 1 1 1 1 1 1 1 1 0 0 11 1 1 0 0 1 1 1 1 0 1 0 x x x x x x x 1 1 0 1 1 x x x x x x x 1 1 1 0 0 x x x x x x x 1 1 1 0 1 x x x x x x x 1 1 1 1 0 x x x x x x x 1 1 1 1 1 x x x x x x x BCD decoder a b c d e f g

12. The k th output is 1 if the n-bit input has binary value of k Ex: 2-to-4 decoder Binary n-to-2 n decoders

13. 2-to-4-decoder logic diagram

14. F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z 3-to-8 binary decoders

15. Idea: Canonical sum (of minterms) = decoder outputs connect to OR gate Canonical sum (of minterms) = decoder outputs connect to OR gate Good and simple implementation when the circuit has many outputs each has few minterms Example: Full adder S(C in, A, B) =  (1,2,4,7) S(C in, A, B) =  (1,2,4,7) C(C in, A, B) =  (3,5,6,7) C(C in, A, B) =  (3,5,6,7) Realizing digital logic using decoders 3-to-8 Decoder S2S1S0S2S1S0 C in A B 0123456701234567 S C ABCS 00000 00101 01001 01110 10001 10110 11010 11111

16. Encoders (vs. decoders) m inputs, n outputs, m>n Ex: 2 n –to-n binary encoder DecoderEncoder

17. I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 Y 0 = I 1 + I 3 + I 5 + I 7 y 1 = I 2 + I 3 + I 6 + I 7 Y 2 = I 4 + I 5 + I 6 + I 7 8-to-3 encoder example What if all I k =0?

18. Multiplexers Digital switches that select one of the n b-bit data as the output

19. 2-input multiplexer using CMOS transmission gates

20. muxY Inputs select S 1 S 0 I0I0 I1I1 I2I2 I3I3 4:1 MUX Y Inputs select S 1 S 0 I0I0 I1I1 I2I2 I3I3 01230123 Output 4-to-1 multiplexer

21. S1S1 S0S0 0 1 2 3 2-to-4 Decoder I0I0 I1I1 I2I2 I3I3 Y S1S1 S0S0 I0I0 I1I1 I2I2 I3I3 Y 4-to-1 Mux circuit diagram

22. Can be constructed using smaller ones … Ex: 8=to-1 Mux 4:1 MUX I0I1I2I3I0I1I2I3 S 1 S 0 4:1 MUX I4I5I6I7I4I5I6I7 S 1 S 0 2:1 MUX S2S2 Y Larger multiplexers

23. 16-to-1 multiplexer

24. 74151A 8-to-1 multiplexer MSI multiplexer example

25. Digital switches that connect the input to one of n outputs Typically n = 2 s Demultiplexers s bits Select b bits.... Data Input Demux n outputs Mux Output Inputs Select

26. DemuxData D Outputs select S 1 S 0 Y 0 = D·S 1 '·S 0 ' Y 1 = D·S 1 '·S 0 Y 2 = D.S 1 ·S 0 ' Y 3 = D.S 1 ·S 0 2x4 Decoder D S1S0S1S0 Y 0 = D·S 1 '·S 0 ' Y 1 = D·S 1 '·S 0 Y 2 = D·S 1 ·S 0 ' Y 3 = D·S 1 ·S 0 E 1-to-4 demultiplexer Implementing n-output b-bit Demux using b n- output Decoders Connecting data bits to enables Connecting data bits to enables Can we do it for Mux using Encoder?

27. Mux-Demux application example Enables number of sources and destinations sharing a single communication channel

28. Implementing n-variable func. using 2 n -to-1 Mux Methodology: Express function in canonical sum form Express function in canonical sum form Connect the n input variables to the Mux select lines, Connect the n input variables to the Mux select lines, For each Mux data input line I i ( 0  i  2 n – 1 ): For each Mux data input line I i ( 0  i  2 n – 1 ): Connect 1 to I i if i is a minterm of the function, Otherwise, connect 0 to I i. Ex: F(X,Y,Z) =  (1,3,5,6) mux X Y Z 0123456701234567 0101011001010110 F Mux Select Lines Mux Data Input Lines

29. Idea: Use only n-1 variables at the select lines Use only n-1 variables at the select lines Connect the last one and its inverse to the input lines Connect the last one and its inverse to the input lines Ex: F(X,Y,Z) =  (0,1,3,6) Implementing n-variable func. using 2 n-1 -to- 1 Mux Mux X Y 01230123 1010 F Z Mux Select Lines Mux Data Input Lines

30. F(x 1,x 2,x 3,x 4 ) =  (0,1,2,3,4,9,13,14,15) using a 8-to-1 Mux ( 74151A ) and an inverter. Another example

31. 1.Express function F in canonical sum form 2.Choose n-1 variables connecting to mux select lines 3.Construct the truth table via grouping inputs based on select line values 4.Determine multiplexer input line i values by comparing the last input variable X and F: Four possible mux input line i values: Four possible mux input line i values: 0 if F=0 regardless of the value of X 1 if F=1 regardless of the value of X F=XF=X’ Implementing n-variable func. using 2 n-1 -to- 1 Mux

32. Barrel shifter design example n data inputs, n data outputs Control inputs specify number of positions to rotate or shift data inputs Example: n = 16 DIN[15:0], DOUT[15:0], S[3:0] (shift amount) DIN[15:0], DOUT[15:0], S[3:0] (shift amount) Many possible solutions, all based on multiplexers