1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 3: Structural Modeling Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l Labs start next week l HW#1 Due in Tuesday » Please put the section number next to your name! » Problem 2 (a) and (b) –Please convert to binary manually » Problem 7 –See Sutherland, section 19.0 for an example of the `define compiler directive

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l What characters are allowed in identifiers? l What kinds of circuits would generate the values 0, 1, x, and z? l What is the difference between wire and reg variables? l What parts of the module description do you need to create a test-bench?

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Parts of a Verilog Module l Header: module ( ); l Parameter, Port, & Variable declarations l Functionality description » Structural –Instantiations of basic gates –Instantiations of lower-level modules » Behavioral –Data-Flow (continuous assignments) –Procedural (initial & always blocks) l Terminator: endmodule

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 wire vs. reg l An easy way to understand the difference between wire and reg variables: l The right-hand side may contain wires or reg’s If the functionality description is… Then the left-hand side of an assignment must be a… Structural (basic gate or module instantiations) wire Data-Flowwire Proceduralreg

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Today’s Lecture l Gate-Level Modeling l Hierarchy l Demuxes and Decoders

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Gate-Level Modeling l Gate-level modeling is the lowest level of design description in Verilog. l Verilog models at the gate level consists of directly specifying the interconnections of fundamental logic elements (AND, OR, etc.). l The available logic elements at the gate level are: and, nand, or, nor, xor, xnor, not, buf, notif & bufif. (All these are keywords.) » What is the significance of a keyword?

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Gate Instantiation l By declaring a series of instances, we can describe a gate-level structure l The basic format of a gate-level instantiation is: (, ); l Instance name is optional l Write out the following instantiations:

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Gate Instantiation

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 2-to-1 Multiplexer x1 n_sel x2 out 2-to-1 Mux i0 i1 sel i0 sel i1 out Write the module header, port & variable declarations:

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 2-to-1 Multiplexer x1 n_sel x2 i0 sel i1 out Write the instantiations and terminator:

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 2-to-1 Multiplexer So the complete module description is: Where are the Instance Names?

13. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Today’s Lecture l Gate-Level Modeling l Hierarchy l Demuxes and Decoders

14. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 4-bit Multiplexer Consider a 4-bit 2-to-1 multiplexer: mux_2 A[2] B[2] Out[2] mux_2 A[1] B[1] Out[1] mux_2 A[0] B[0] Out[0] sel mux_2 A[3] B[3] Out[3] Which can be constructed with four 2-to-1 multiplexers. 4-bit mux A B sel Out 4 4 4

15. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Module Instantiation l Module instantiation looks the same as gate-level instantiation: ( ); l Port list follows same order as module header module mux_2 (out, i0, i1, sel); l Instance name is optional, but I suggest you use it » Why? Because you can examine a modules internal signals in the test-bench using the syntax: instance_name.signal_name

16. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 4-bit Multiplexer mux_2 A[2] B[2] Out[2] mux_2 A[1] B[1] Out[1] mux_2 A[0] B[0] Out[0] sel mux_2 A[3] B[3] Out[3] Write the module header, port & variable declarations:

17. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 4-bit Multiplexer m3 m2 m1 m0 mux_2 A[2] B[2] Out[2] mux_2 A[1] B[1] Out[1] mux_2 A[0] B[0] Out[0] sel mux_2 A[3] B[3] Out[3] Write the instantiations and terminator:

18. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Alternative Port-List Format Using the 4-bit multiplexer as an example, the instantiations could be written as: mux_2 m3(.sel(sel),.i0(A[3]),.i1(B[3]),.out(Out[3])); mux_2 m2(.i0(A[2]),.i1(B[2]),.out(Out[2]),.sel(sel)); Alternatively, a port-list can contain a list of port-name references with the following format:. ( ) This is more verbose, but the port-order doesn’t matter.

19. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 4-bit Multiplexer So the complete module description is: How would you reference signal x1 in instance m2? Is sel a reg or a wire? What would happen if you declared sel… as a wire? as a reg?

20. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Port Connection Rules l Verilog has rules about what kinds of variables can be connected to certain ports (see T&M 1.4.4, S&F 2.3.1) » assignment in procedural blocks are made to reg variables » all other assignments are made to net (wire) variables l As a result, there are restrictions on the variables used for port connections, as illustrated below: port in a module port on an instance inputnetreg | net outputreg | netnet inoutnet

21. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Port Connection Rules l An intuitive way to think about it: » A reg cannot be connected to a port that is considered to be a “driver” » The following ports are considered to be drivers: –input port in a module –output port on an instance –inout port, both in a module and on an instance

22. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Port Connection Rules l Which signals cannot be declared as reg? x1 n_sel x2 i0 sel i1 out

23. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Today’s Lecture l Gate-Level Modeling l Hierarchy l Demuxes and Decoders

24. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Demultiplexer l A demultiplexer (DEMUX) passes a single input to one of many output lines, depending on a control input sz0z1 0in0 10 Draw a gate-level schematic for a DEMUX:

25. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 Larger DEMUXes l Cascade Smaller DEMUXes to make larger ones

26. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 Decoder l A decoder sets one output line high and all others low, depending on an input signal sz0z1 010 101 How can you turn a DEMUX into a decoder?

27. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 Summary l What is the format of a Verilog instantiation? l Are all parts of the instantiation required? l What is the order of the port-names in a gate instantiation? A module instantiation? l Can a reg variable be connected to the input port of an instance?