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Shannon decomposition William Sandqvist Claude Shannon mathematician / electrical engineer (1916 –2001) William Sandqvist

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Presentation on theme: "Shannon decomposition William Sandqvist Claude Shannon mathematician / electrical engineer (1916 –2001) William Sandqvist"— Presentation transcript:

1 Shannon decomposition William Sandqvist william@kth.se Claude Shannon mathematician / electrical engineer (1916 –2001) William Sandqvist william@kth.se (Degital Design Ex4)

2 (Ex 8.6) Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function.

3 William Sandqvist william@kth.se (Degital Design Ex4) (Ex 8.6) Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function. Multiplexer as function generator

4 William Sandqvist william@kth.se (Degital Design Ex4) (Ex 8.6) = Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function. Multiplexer as function generator

5 William Sandqvist william@kth.se (Degital Design Ex4)

6 BV 6.1 Show how the function can be implemented using a 3-to-8 decoder and an OR gate.

7 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.1 Show how the function can be implemented using a 3-to-8 decoder and an OR gate.

8 William Sandqvist william@kth.se (Degital Design Ex4)

9 Ex 8.7 A majority gate outputs the same value as the majority of the inputs. The gate can for example be used in fault-tolerant logic, or in image processing circuits. a) (Set up the gate's truth table and minimize the function with Karnaugh map. Realize the function with AND-OR gates. ) b) Realize the majority gate with an 8: 1 MUX. c) Use Shannon decomposition and realize the majority gate with a 2: 1 MUX and gates. d) Realize the majority gate with only 2:1 MUXes.

10 William Sandqvist william@kth.se (Degital Design Ex4) (8.7a) With AND OR gates

11 William Sandqvist william@kth.se (Degital Design Ex4) (8.7a) With AND OR gates

12 William Sandqvist william@kth.se (Degital Design Ex4) (8.7a) With AND OR gates

13 William Sandqvist william@kth.se (Degital Design Ex4) (8.7a) With AND OR gates

14 William Sandqvist william@kth.se (Degital Design Ex4) 8.7b With 8-to-1 mux …

15 William Sandqvist william@kth.se (Degital Design Ex4) 8.7b With 8-to-1 mux …

16 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c Shannon decomposition. 2-to-1 mux and gates.

17 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c Shannon decomposition. 2-to-1 mux and gates.

18 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c Shannon decomposition. 2-to-1 mux and gates.

19 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c OR Shannon decomposition. 2-to-1 mux and gates.

20 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c OR Shannon decomposition. 2-to-1 mux and gates.

21 William Sandqvist william@kth.se (Degital Design Ex4) 8.7c OR Shannon decomposition. 2-to-1 mux and gates.

22 William Sandqvist william@kth.se (Degital Design Ex4) 8.7d Shannon decomposition. Only 2-to-1 muxes.

23 William Sandqvist william@kth.se (Degital Design Ex4) 8.7d Shannon decomposition. Only 2-to-1 muxes.

24 William Sandqvist william@kth.se (Degital Design Ex4) 8.7d Shannon decomposition. Only 2-to-1 muxes.

25 William Sandqvist william@kth.se (Degital Design Ex4) 8.7d Shannon decomposition. Only 2-to-1 muxes.

26 William Sandqvist william@kth.se (Degital Design Ex4)

27 BV 6.5 William Sandqvist william@kth.se For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. William Sandqvist william@kth.se (Degital Design Ex4)

28 BV 6.5 William Sandqvist william@kth.se For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. William Sandqvist william@kth.se (Degital Design Ex4)

29 BV 6.5 William Sandqvist william@kth.se For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. William Sandqvist william@kth.se (Degital Design Ex4)

30 BV 6.5 William Sandqvist william@kth.se For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. William Sandqvist william@kth.se (Degital Design Ex4)

31

32 (Ex 8.9) Show how one four-input exorgate (XOR, odd parity function) is realized in an FPGA circuit. Show the contents of the SRAM cells ( LUT, Lookup Table )

33 William Sandqvist william@kth.se (Degital Design Ex4) (8.9)

34 William Sandqvist william@kth.se (8.9) William Sandqvist william@kth.se (Degital Design Ex4)

35 William Sandqvist william@kth.se (8.9) William Sandqvist william@kth.se (Degital Design Ex4)

36 (Ex 8.8) Set up full adder truth table. Show how a full adder is implemented in an FPGA chip. Logic elements of an FPGA is able to cascade COUT and CIN between "neighbors." Show the contents of the SRAM cells ( LUT, Lookup Table ).

37 William Sandqvist william@kth.se (Degital Design Ex4) (8.8)

38 William Sandqvist william@kth.se (Degital Design Ex4) (8.8)

39 William Sandqvist william@kth.se (8.8) William Sandqvist william@kth.se (Degital Design Ex4)

40 William Sandqvist william@kth.se (8.8) William Sandqvist william@kth.se (Degital Design Ex4)

41 (BV ex 6.31) In digital systems it is often necessary to have circuits that can shift the bits of a vector one or more bit positions to the left or right. Design a circuit that can shift a four-bit vector W = w 3 w 2 w 1 w 0 one bit position to the right when a control signal Shift is equal to 1. Let the outputs of the circuit be a four-bit vector Y = y 3 y 2 y 1 y 0 and a signal k, such that if Shift = 1 then y 3 = 0, y 2 = w 3, y 1 = w 2, y 0 = w 1, and k = w 0. If Shift = 0 then Y = W and k = 0.

42 William Sandqvist william@kth.se (Degital Design Ex4)

43 We uses MUXes: (BV ex 6.31)

44 William Sandqvist william@kth.se (Degital Design Ex4) (BV ex 6.31) We uses MUXes:

45 William Sandqvist william@kth.se (Degital Design Ex4)

46 BV ex. 6.32 Barrel shifter The shifter in Example 6.31 shifts the bits of an input vector by one bit position to the right. It fills the vacated bit on the left side with 0. If the bits that are shifted out are placed into the vacated position on the left, then the circuit effectively rotates the bits of the input vector by a specified number of bit positions. Such a circuit is called a barrel shifter. Design a four-bit barrel shifter that rotates the bits by 0, 1, 2, or 3 bit positions as determined by the valuation of two control signals s 1 and s 0. A barrelshifter is used to speed up floating point operations.

47 William Sandqvist william@kth.se Barrel shifter William Sandqvist william@kth.se (Degital Design Ex4)

48 BV ex. 6.32 Truth table: W0 W1 W2 W3 01230123

49 William Sandqvist william@kth.se (Degital Design Ex4) BV ex. 6.32 Truth table: W0 W1 W2 W3 01230123

50 William Sandqvist william@kth.se (Degital Design Ex4) BV ex. 6.32 Truth table: W0 W1 W2 W3 01230123

51 William Sandqvist william@kth.se (Degital Design Ex4) BV ex. 6.32 Truth table: W0 W1 W2 W3 01230123

52 William Sandqvist william@kth.se (Degital Design Ex4) BV ex. 6.32 Truth table: W0 W1 W2 W3 01230123

53 William Sandqvist william@kth.se (Degital Design Ex4) BV ex. 6.32 And so on... Truth table: W0 W1 W2 W3 01230123

54 William Sandqvist william@kth.se (Degital Design Ex4)

55 = Lowcost FPGA William Sandqvist william@kth.se (Degital Design Ex4) Key Benefits  Lowest FPGA unit cost starting at $0.49  Ultra-low power in Flash*Freeze mode, as low as 2 µW  Nonvolatile FPGA eliminates unnecessary parts from BOM  Single-chip and ultra-low-power products simplify board design  Variety of cost-optimized packages reduce assembly costs  Low-power FPGAs reduce thermal management and cooling needs

56 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.16 Actel Corporation manufactures an FPGA family called Act 1, which uses multiplexer based logic blocks. Show how the function can be implemented using only ACT 1 logic blocks.

57 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.16

58 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.16

59 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.16

60 William Sandqvist william@kth.se (Degital Design Ex4) BV 6.16

61 William Sandqvist william@kth.se (Degital Design Ex4)

62 VHDL BV 2.51a Write VHDL code to describe the following functions VHDL code is written with a text editor and saved in a file with the extension.vhd. The code always consists of two sections ENTITY and ARCHITECTURE. Entity is a description of how the circuit "looks from the outside" (the interface), and Architecture how it "looks like inside."

63 William Sandqvist william@kth.se (Degital Design Ex4) VHDL BV 2.51a Comments begin with –- If you wish, you can "draw" clarification ASCII graphics in the comment lines.. -- ___________ -- | | -- | Functions | -- ->-| x1 | -- ->-| x2 f1 |->- -- ->-| x3 f2 |->- -- ->-| x4 | -- |___________| -- Program code is written with a text editor. So we can only do text comments to the code. A fixed-width font is used ( eg. Courier New ). One usually indent text blocks that belong together for greater clarity.

64 William Sandqvist william@kth.se (Degital Design Ex4) VHDL BV 2.51a ENTITY Functions IS PORT(x1, x2, x3, x4 :IN STD_LOGIC; f1, f2, :OUT STD_LOGIC ) END Functions ARCHITECTURE LogicFunc OF Functions IS BEGIN f1 <= (x1 AND NOT x3)OR(x2 AND NOT x3)OR (NOT x3 AND NOT x4)OR(x1 AND x2)OR (x1 AND NOT x4); f2 <= (x1 OR NOT x3)AND(x1 OR x2 OR NOT x4)AND (x2 OR NOT x3 OR NOT x4); END LogicFunc ;

65 VHDL BV 6.21 William Sandqvist william@kth.se (Degital Design Ex4) Using a selected signal assignement, write VHDL code for a 4-to-2 binary encoder. Only one of w0 …w3 is ”1” at a time. LIBRARY ieee; USE IEEE.std_logic_1164.all; ENTITY ENCODER IS PORT( w :IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ) ; y :OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ); END ENCODER ARCHITECTURE Behavior OF ENCODER IS BEGIN WITH w SELECT y <= ”00” WHEN ”0001”, ”01” WHEN ”0010”, ”10” WHEN ”0100”, ”11” WHEN OTHERS; END Behavior ;

66 William Sandqvist william@kth.se (Degital Design Ex4)

67 (8.10) Additional if time permits William Sandqvist william@kth.se (Degital Design Ex4) Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1

68 Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1 Y

69 Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1 x0x0 x1x1 0101 0 1 x0x0 x1x1 0101 x0x0 x1x1 0101 x0x0 x1x1 0101 Y William Sandqvist william@kth.se (Degital Design Ex4)

70 Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1 -- 10 x0x0 x1x1 0101 0 1 01 01 x0x0 x1x1 0101 01 10 x0x0 x1x1 0101 -- 10 x0x0 x1x1 0101 Y William Sandqvist william@kth.se (Degital Design Ex4)

71 Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1 -- 10 x0x0 x1x1 0101 0 1 01 01 x0x0 x1x1 0101 01 10 x0x0 x1x1 0101 -- 10 x0x0 x1x1 0101 Y William Sandqvist william@kth.se (Degital Design Ex4)

72 Y -- -- 1 0 0 0 0 0 0 1 1 1 1 1 -- 10 x0x0 x1x1 0101 0 1 01 01 x0x0 x1x1 0101 01 10 x0x0 x1x1 0101 -- 10 x0x0 x1x1 0101 Y William Sandqvist william@kth.se (Degital Design Ex4) Or … Or if you don’t have acess to the variable x 0 inverted …

73 William Sandqvist william@kth.se (Degital Design Ex4)

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