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ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006.

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Presentation on theme: "ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006."— Presentation transcript:

1 ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006

2 Contributions I have taken some of the slides in this tutorial from Jeff Wentworth’s ASIC 120

3 Digital vs Analog Analog: Continuous time varying signal. –Application: Radio Digital: Abstraction. Two signals: 0 and 1. –Application: Computer Processors

4 Switches Switches are the basic building block of Digital hardware Have 2 states: –On = 1, Off = 0 Can be electrically controlled: –Ex. Relay, Vacuum Tube, Transistor

5 Transistor Used in all modern digital hardware 3 Terminal Device Operation: –If C is high voltage (1) then current flows between A and B Transistor A B C Wires

6 Logic Gates 2-input, 1-output devices Simpler than working with switches directly Inverter (NOT gate): AX 01 10 InputOutput Truth Table

7 Inverter Implementation When Input is 1: –Transistor 1: off –Transistor 2: on –Output: 0 (ground) When Input is 0: –Transistor 1: on –Transistor 2: off –Output: 1 (5V) Transistor 1 5 V (1) Input Output Transistor 2 Ground (0)

8 Combinational Logic: AND ABX 000 010 100 111

9 Combinational Logic: OR ABX 000 011 101 111

10 Combinational Logic: XOR ABX 000 011 101 110

11 Combinational Logic: NAND ABX 001 011 101 110

12 Combinational Logic: NOR, XNOR ABX 001 010 100 110 ABX 001 010 100 111

13 Building Combinational Circuits ABCX 0000 0100 1001 1101 0010 0111 1010 1111

14 Combinational Logic: MUX (multiplexer) ABCX 0000 0100 1001 1101 0010 0111 1010 1111

15 MUXs A MUX can be thought of as an if statement. If C = 0 then X = A Else if C = 1 then X = B This will be useful later

16 Binary Addition Adding 2 bits: –0+0=0 –0+1=1 –1+0=1 –1+1=10 So we need 2 inputs and 2 outputs

17 Half Adder ABSC 0000 0110 1010 1101

18 Full Adder (3-bit addition)

19 Independent Tasks Modelsim – VHDL hardware simulator –Download evaluation copy from: http://www.model.com/downloads/evaluation s.asp Quartus II – FPGA Synthesis Tool –Download Web Edition from: http://www.altera.com/products/software/pro ducts/quartus2web/sof-quarwebmain.html

20 Development Boards For interested students there are development boards available Check out the DE2: http://www.altera.com/education/univ/mate rials/boards/unv-de2-board.html http://www.altera.com/education/univ/mate rials/boards/unv-de2-board.html The DE2 comes with lab exercises and design examples Not cheap: $269 US

21 Quartus II Exercise Open Quartus II, Select File->New Project Wizard, Select a valid working directory (should be an empty folder) Name the project and entity “half_adder” Click next for all other menus Select File->New. Select VHDL File

22 Quartus II Exercise Cont Save the file as half_adder.vhd, with the contents: library ieee; use ieee.std_logic_1164.all; entity half_adder is Port ( i_A, i_B : in STD_LOGIC; o_Sum, o_Carry : out STD_LOGIC ); end half_adder; architecture main of half_adder is begin o_Sum <= i_A xor i_B; o_Carry <= i_A and i_B; end main;

23 Quartus II Exercise Cont Select Processing->Start->Analysis and Synthesis Make sure it completes successfully Next Step –Read through the help file under “simulation” –Try Simulating the design

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