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Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4.

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Presentation on theme: "Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4."— Presentation transcript:

1 Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 4

2 Abstract Today’s class:  Gate level modeling  Examples

3 Gate-Level Modelling Primitive logic gates ( 基本邏輯閘 ) are part of the Verilog language. Build-in logic models (gate stands for one of the keywords): –Basic gates: and, nand, or, nor, xor, xnor (not xor) (see Fig.4-1) –Buffers and inverter gates: buf, not (see Fig. 4-2) –Three-state gates: bufif1 (buf if 1), bufif0 (buf if 0), notif1 (not bufif1), notif0 (not bufif0) (see Fig.4-3) User-defined primitives (UDP) is defined as module instantiations Syntax: gate (drive_strength) #(delays) instance_name1(output,input_1,…,input_N), instance_name2(output,input_1,…,input_N); –Instance name can be ignored. –Drive strength::=(pull-up,pull-down) defaults ::= (strong1,strong0) (see Table 3-1 for details) –Delay ::= #(rise,fall) or #rise and fall or #(rise and fall)

4 AND3 and_outin1in2in3 0000 0001 0010 0011 0100 0101 0110 1111

5 Or3 or_outin1in2in3 0000 1001 1010 1011 1100 1101 1110 1111

6 NAND2 nand_outin1in2 100 101 110 011

7 nor_outin1in2 100 001 010 011 NOR2

8 XOR xor_outin1in2 000 101 110 011

9 XNOR2 XOR2 xnor_outin1in2 100 001 010 111

10 BUFIF1 bufif1_outinctrl z00 001 z10 111

11 BUFIF0 bufif0_outinctrl 000 z01 110 z11

12 NOTIF1 notif1_outinctrl z00 101 z10 011 p.s.: inverse of bufif1

13 NOTIF0 notif0_outinctrl 100 z01 010 z11 p.s.: inverse of bufif0

14 deco2_4

15 Com1_g 1-bit Comparator

16 Method 1: gate instantiation Method 2: bit-wise operator 2-bit Comparator (comp2_g)

17 mux2_1g 1-bit 2-1 multiplexer

18 Data Output from D-type Flip Flop using 2-1 Multiplexer dff_sel

19 mux4_1g Logic Gates 1-bit 4-1 multiplexer (method 1)

20 mux4_1b_g bufif0 & bufif1 1-bit 4-1 multiplexer (method 2)

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