1. 1 ECNG 1014: Digital Electronics Combinational Circuits

2. 2 Logic Device Classification Combinational Circuit output is a function only of the current inputs eg., AND gates, decoders Sequential Circuit output is a function only of the current inputs AND past inputs i.e. the circuit has memory. Eg. counters Small Scale Integration (SSI) Integrated circuit uses only a few gates (20 or less). Typically provides only basic gate functions Medium Scale Integration (MSI) IC uses 20-200 gates to provide common higher level functions such as decoding, multiplexing, counting etc. Large Scale Integration (LSI) Ics have 200-200K gates ( 400K transistors) or more to realise still higher functions such as small memories and microprocessors, PLDs, CPLDs etc. Very Large Scale Integration (VLSI) IC with over 10 6 transistors or more which realises the highest level of logic functionality. Examples: Pentium level processors (50 mil xsistors!), FPGAs etc. Device delay (and cost) goes up with complexity

3. 3 Design Procedure for Combinational Circuits State the problem in combinational terms. Determine the required inputs and outputs Derive the truth table. Simplify the output expressions using Boolean laws or k-maps. Implement the output expressions with logic gates. Design example: Implement a logic circuit that detects if an unsigned 4-bit number is prime.

4. 4 Combinational Logic Using MSI and LSI devices Commercial ICs can perform complex functions using a single IC of type MSI or LSI, their characteristics are described in Logic data book (http://www.ti.com, semiconductor logic).http://www.ti.com

5. 5 TTL Device NumberDescription 74834-bit adder with fast carry 74854-bit magnitude comparator 741392-line-to-4-line decoder/demultiplexer 741373-line-to-8-line decoder/demultiplexer 741594-line-to-16-line decoder/demultiplexer 74145BCD-to-Decimal encoder 74147Priority encoder 741518 x 1 multiplexer 7415016 x 1 multiplexer 74184BCD-to-binary converter 742809-bit odd/even parity generator

6. 6 Decoders (5.4.1-5.4.5) General decoder structure A decoder is a MIMO device that maps an input code to a different unique output code, I.e. the mapping is 1-to-1 Typically n inputs, 2 n outputs 2-to-4, 3-to-8, 4- to-16, etc Most common: Binary Decoder maps each n- bit input to assert only 1 of 2 n outputs Also: 7-segment and BCD decoders

7. 7 Binary decoder applications Microprocessor memory systems –selecting different banks of memory Microprocessor input/output systems –selecting different devices (printer, serial, video etc) Microprocessor instruction decoding –enabling different functional units within the uP. Memory chips –enabling different rows of memory depending on inputted address Identifying or selecting various circuit options. Can also be used for logic synthesis since each output actually represents a unique minterm of the inputs…….

8. 8 Binary 2-to-4 decoder Enable input Once Enabled, ONLY the k’th logic output (k:0, 1,..2 n -1) is asserted when the input binary word satisfies: I 1 I 0 = k … the k’th minterm!! => ¡¡ Y 0 = m o, Y 1 =m 1, … Y i =m i !! x = don’t care.

9. 9 SO… can use to synthesise all logic functions of n variables!! E.g. Realise F=  X,Y (0,3) using a 74x139 2-4 decoder F YXYX 0 Bubble Active low enable Select inputs: B is the MSB in the select word i.e. BA The 1/2 => the 74139 has TWO (independent) decoders. Only using 1 of them Most decoders use Active Low outputs => faster

10. 10 Complete 74x139 Decoder All Inputs buffered to minimise loading

11. 11 b2 b0 b1 DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L How do we get a larger decoder? Cascade smaller ones…. Use MSB(‘s) to select one decoder (for one part of the Truth Table) Use lower SB’s to select the output The “_L “ is a standard nomenclature for an active low signal line Upper half of TT (b2=0) Lower half of TT (b2=1)

12. 12 Or.. We can use an off-the-shelf device, if available 74x138 3-to-8-decoder C is MSB EN = (G1)(G2A)’(G2B)’

13. 13

14. 14 MC6809uP Data (8) Address (16) Control 16K RAM Data Address CS 16K RAM Data Address CS 16K RAM Data Address CS 16K RAM Data Address CS A15, A14 2 2-4Y0 Address Y1 DecoderY2 Y3 8 To all memory data pins To all memory address pins A 0-13 14 R/W: Connected to Memory R/W to control data direction The decoder selects only 1 of the 4 banks at a time for data bus connection. Specific words are determined by the lower 14 address lines connected to the memory device’s address inputs 8 8 8 8 A 0-13

15. 15 Address Bit: 1514131211109876543210 0000 16 0000000000000000 3FFF 16 0011111111111111 4000 16 0100000000000000 7FFF 16 0111111111111111 8000 16 1000000000000000 BFFF 16 1011111111111111 C000 16 1100000000000000 FFFF 16 1111111111111111 Bank0: A 14 =A 15 =0 Bank1: A 15 =0.A 14 =1 Bank2: A 15 =1.A 14 =0 Bank2: A 15 =1.A 14 =1 FIXED for each bank Internal Memory Address Lines Decoder Design Work Sheet

16. 16 Comparators The basic function of a comparator is to compare the magnitude of two binary quantities to determine the relationship of those quantities. In its simplest form, a comparator circuit determines whether two numbers are equal. A 1-bit comparator is implemented as:

17. 17 A complex comparator can be implemented taking into account inequality. For two numbers A and B, we will have to consider ( A = B, A B). The following figure gives a block diagram of a 4-bit comparator: 4 4 A[3:0] B[3:0] A>B A=B A>B 4-bit Comparator

18. 18 For the Output A > B to be active, we must have these conditions: - If A3 = 1 and B3 = 0, (A3'B3) then A >B - If A3 = B3 and A2 = 1(condition x3 for equality between A3 and B3) and A2 = 1 and B2 = 0, (x3A2B2'), then A >B etc The 74X85 (X = LS, HC, or ALS) is a 4-bit comparator.

19. 19 Encoders An n-input binary encoder is a logic circuit that, given an n-bit input word X that contains one active signal xi, generates and output word Z, which is a binary representation of i, the index of the active input signal. Thus an encoder is the inverse of a decoder, and typically has n = 2 k input lines of X and k output lines for Z. A four-input encoder, for instance, has n = 4 and k = 2, and maps the input combinations 1000, 0100, 0010, and 0001 onto the output combinations 00, 01, 10, and 11 respectively.

20. 20 A Binary Encoder

21. 21 An encoder is intended to identify a single active input signal. However there is nothing to prevent several of its X input lines from being active at the same time, because they may be driven from independent external sources. To deal with this situation, most encoders are designed as priority encoders, which have the property that when several inputs are active at the same time, the output number I that appears on Z is the index of the input line xi with the highest priority. The following figures give the block diagram and logic equations of a priority encoder.

22. 22 Block Diagrams Logic equations

23. 23 ECNG 1014: Digital Electronics Combinational Devices: Pt 2 - Multiplexers Section 5.7, Wakerly

24. 24 A What? A multiplexer (mux) is a device that allows us to select one of n- sets of b-bit data for transmission to its b-bit output. It is a digital switch.

25. 25 E.g. 74151 8input x 1 bit MUX EN A B C D0Y D1Y D2 D3 D4 D5 D6 D7 74x151 Select Inputs Data Inputs If EN = 1 Then Y=0 Else k = val(CBA) Y=D k Endif Y=EN  m k D k, where m k is the k’th minterm of select word CBA. EN_L

26. 26 2-input, 4-bit-wide 74x157 For I=1 to 4 If G=0 Then iY = 0 Else If S=0 Then iY=iA Else iY=iB Endif Endfor G S 1A1Y 1B 2A2Y 2B 3A3Y 3B 4A4Y 4B 74x157 E.g. iY = G(S’iA + S iB), i=12,3,4

27. 27 As for decoders, can use MUXes to synthesise logic E.g. Implement F=ab’+a’d+abc’ on a 2-1mux Solution: With 2 inputs, D0 and D1, say, the MUX will have 1 select input, SEL, say. Step 1: Choose variables for direct connection to the select inputs. This can be arbitrary but note that, as in all things, the actual choice will affect the amount of work required to complete the design Let SEL = a, say Step 2: Using expression for F, which will be the MUX output, select appropriate logic functions of remaining variables to drive the MUX data inputs. This may be derived by comparison of the MUX expression and the target logic function or from the function’s truth table SEL D0Y D1 a d b’+c’ F F= Y = SEL’D0 + SEL D1 => F = D0 if SEL=0 OR F=D1 if SEL=1 D0 = F| SEL=0 D0 = F| a=0 = d Similarly, D1 = F| a=1 = b’+bc’ =b’+c’

28. 28 E.g. Use a Kmap to realise F= WXZ’ + WX’Y + XZ on an 8-1 MUX. Step 1: There will be 3 select inputs (why?) SEL0, SEL1, SEL2. Let: W=SEL2, X=SEL1, Y=SEL0. 00000110111100110000011011110011 00 01 WX 11 10 YZ 00011110 D0 = 0 D1 = 0 D3 = Z D7 = 1 D5 = 1 D4 = 0 D2 = Z D6 = 1 Step 2: From the K-map determine each input as a logic function of the remaining variable (Z): e.g.: To determine the function to be applied to D3 note that D3 is selected when W=0, X=1, Y=1. Now, identify all those cells for which WXY=011. Write the logic values in these cells as a function of the remaining variable, Z.

29. 29 EN A B C D0Y D1Y D2 D3 D4 D5 D6 D7 74x151 0YXW00ZZ01110YXW00ZZ0111 F= WXZ’ + WX’YZ + XZ On a 74151 ….. Note: No logic gates required!! Exercise: Verify that this works by referring to the operation of the 74151 MUX

30. 30 00000110111100110000011011110011 00 01 WX 11 10 YZ 00011110 S0 S1 D0 Y D1 D2 D3 Y Z F Same Function on a 4-1 MUX

31. 31 Theorem on MUX realisations: A 2 n - to-1 MUX can be used to realise ALL (n+1)-variable logic functions without the use of logic gates (save for inverters). Proof: A 2 n - to-1 MUX will have n select lines. Take any n of the variables, X 0 - X n-1, and connect them individually to these n select lines (step 1!). For each of the 2 n - select combinations, the function value will depend only on the value of the last variable, X n (step 2!) and could therefore assume one of the 4 possible functions of this one variable: 0, 1, X n, X n ’. The function is therefore realised by appropriately connecting any one these 4 functions of the last variable to the data inputs.

32. 32 MUX uses As a data selector (original purpose) Not generally used for logic realisation using MSI components but… used as the core of combinational logic in some LSI and VLSI devices such as Field Programmable Gate Arrays (FPGAs). FPGAs exploit the MUX Theorem to allow general users to implement logic functions at VLSI density at a very low cost.

33. 33 Demultiplexers A demultiplexer basically reverses the multiplexing function. It takes data from one line and distributes them to given number of output lines. A demultiplexer has N = 2 k output lines, k address selection and one data line. The number of the output line active is specified by the k bits address.

34. 34 2 n outputs n-bit selections input 1 x 2 n DEMUX Demultiplexer

35. 35 ECNG 1014: Digital Electronics Combinational Devices: ROMs

36. 36 Why “ROM”? Program storage –Boot ROM for personal computers –Complete application program storage for embedded microprocessor systems. Actually, a ROM is a combinational circuit, basically a truth-table lookup. –Can perform any combinational logic function –Address inputs = function inputs –Data outputs (stored data) = function outputs

37. 37 ROM Internal Structure Internal array of (address) word and (data) bit lines Each intersection of word and bit lines interconnected by an element that can be “programmed” to be open or short circuited Each word line is activated from the address via decoder Each bit line outputs a logic level corresponding to the state of the interconnection with an activated word line Memory array E.g. A ROM Modern memories use MOS transistors as interconnection elements. In this example, a fully connected transistor at the intersection of an activated word line and a bit line results in a stored 0 (actually a 1 since the bit lines are usually buffered via an inverter to the corresponding data output). A disconnected transistor results in a stored 1 (a 0 at the output).

38. 38 Two-dimensional decoding Accommodates large address widths in a more compact form Uses a decoder and MUX to select bits S0 S1 A0A1A0A1 Y D0 A2A2 A n-1 2D decoding in a 2 n x 1 ROM 2 n bits of storage

39. 39 Larger example, 32Kx8 ROM: Stack for word storage 2 15 =32K address space

40. 40 Programmable and erasable using floating-gate MOS transistors More reliable than fuse based PROMs EPROMs, EEPROMs, Flash PROMs Floating gate is isolated from rest of circuit but can be charged/discharged When discharged, transistor can be turned on by word line When charged transistor cannot be turned on by word line EPROM: floating gate discharged via UV light EEPROM/Flash PROMs: floating gate can be discharged electrically

41. 41 Typical commercial EPROMs

42. 42 EEPROM programming Apply a higher voltage to force bit change –E.g., VPP = 12 V Various bit erase procedures –Byte-byte –Entire chip (“flash”) –One block (typically 32K - 66K bytes) at a time Programming and erasing are a lot slower than reading (milliseconds vs. 10’s of nanoseconds)

43. 43 Microprocessor EPROM application Be cool! Do NOT panic!

44. 44 Full featrured ROM structure (except for programming)

45. 45 Logic-in-ROM example: 2-4 Decoder with polarity control

46. 46 4x4 multiplier example Y Hexadecimal EPROM Listing Row Starting Address XY X Data at Address Location _0 _1 _2 _3 _4 _5 _6 _7 _8 _9 _A _B _C _D _E _F 2*F 16 =2*15 10 =30 10 =1E 16

47. 47 Exercise Determine all the data words stored in the 8x4 PROM of figure 10-5, Wakerly

48. 48 Exercise Determine all the data words stored at A6-0= 0, 5, 29, 120 in the PROM of figure 10-7, Wakerly

49. 49 ECNG 1014: Digital Electronics Combinational Devices: PLDs Wakerly Section 5.3

50. 50 Programmable Logic Arrays (PLAs) Any combinational logic function can be realized as a sum of products. Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. –n inputs AND gates have 2n inputs -- true and complement of each variable. –m outputs, driven by large OR gates Each AND gate has a programmable connection to each output’s OR gate. –p AND gates where (p<<2 n = no. minterms)

51. 51 Example: 4x3 PLA, 6 product terms Programming selectively breaks hardwired connections. These are all fully committed at manufacture AND Array OR Array

52. 52 Compact representation Actually, closer to physical layout (“wired logic”). In this model Default output is a “1”. Must programme “0’s”

53. 53 Some product terms I1’.I2’.I3’.I4’ I1’.I3.I4

54. 54 PLA Electrical Design See Section 5.3.5 -- wired-AND logic Fuse Fuse intact => line can be pulled low when xsistor ON Fuse blown => line remains in default HIGH state when attempt to put xsistor ON Vcc Default HIGH

55. 55 Programmable Array Logic (PALs) PLAs share product terms. How beneficial is product sharing? –Not enough to justify the amount of programmable interconnections PALs ==> fixed OR array –Each AND gate is permanently connected to a certain OR gate. Example: PAL16L8

56. 56 10 primary inputs 8 outputs, with 7 ANDs per output 1 AND for 3-state enable 6 outputs (IO 1-6 )available as inputs –more inputs, at expense of outputs –two-pass logic, helper terms Note inversion on outputs –output is complement of sum- of-products –newer PALs have selectable inversion EPROM as well as original OTP (1-time programmable) versions available

57. 57 Designing with PALs Compare number of inputs and outputs of the problem with available resources in the PAL. Write equations for each output using ABEL or VHDL. Compile the program, determine whether minimized equations fit in the available AND terms. If no fit, try modifying equations or providing “helper” terms.