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Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt 1 FACULTY OF ENGINEERING AND ARCHITECTURE.

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Presentation on theme: "Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt 1 FACULTY OF ENGINEERING AND ARCHITECTURE."— Presentation transcript:

1 Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt Karel.Heyse@UGent.be 1 FACULTY OF ENGINEERING AND ARCHITECTURE Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

2 FPGA configuration I/O block Logic Block Programmable routing 01 0 0 0 1 FF 0 A B O LUTLUT 2 Configuration { 0 0 0 1 0 1 0 0 0 … } Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

3 Parameterized Configuration SpecializedConfigurations { 0 1 0 A+B AB A 1 } { 0 1 0 0 0 0 1 } * K. Bruneel and D. Stroobandt, “Automatic Generation of Run-time Parameterizable Configurations,” FPL 2008. 3 { 0 1 0 1 0 0 1 } { 0 1 0 1 0 1 1 } { 0 1 0 1 1 1 1 } 01 10 11 00 AB Parameters Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

4 Applications Dynamic Circuit Specialization – Circuit optimization (smaller, faster, …) using run- time reconfiguration Circuit Specialization – Hard coded settings of devices Very fast generation of specialized configurations 4Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

5 Static Connections What’s new in this work 5 01 0 A+B A 1 FF 0 A B O LUTLUT Tunable LUTs (TLUT) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

6 Tunable Connections (TCON) AB1 What’s new in this work 6 0 A+B A 1 FF 0 A B O LUTLUT Tunable LUTs (TLUT) Mapping functionality to Tunable Connections (and TLUTs) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

7 Outline FPGA configuration Applications What’s new in this work Toolflow Technology mapping Experiments Conclusion and Future work 7Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

8 Toolflow 88 Parameterized HDL design Parameterized configuration Specialized configuration Parameter values Synthesis Technology mapping PlacementRouting Evaluate Boolean fn. Generic Stage Specialization Stage Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

9 Toolflow 99 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting a0a0 I1I1 I2I2 p O a1a1 a2a2 a3a3 I0I0 a4a4 entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

10 Toolflow 10 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting Tunable LUT network I1I1 I2I2 O I0I0 a0a0 I1I1 I2I2 p O a1a1 a2a2 a3a3 I0I0 a4a4 TLUT Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

11 Toolflow 11 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting TLUT & TCON network I1I1 I2I2 O I0I0 I3I3 C(P)C(P) Tunable Connection (TCON) TCON TLUT TCON Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

12 Toolflow 12 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting p 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬p

13 Toolflow 13 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting 1 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬1

14 Toolflow 14 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting 0 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬0

15 Technology mapping 15 a0a0 I1I1 I2I2 I3I3 O a1a1 a2a2 a3a3 I0I0 a4a4 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

16 Algorithm Minimal depth mapping 1.Cone enumeration: Finding all feasible cones per node 2.Cone ranking: Selecting best feasible cone per nod e 3.Cone selection: Selecting cones that provide covering 16Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

17 Feasibility: LUT Cone with 3 input nodes = LUT-feasible (3 input LUT) 17 a0a0 I1I1 I2I2 a1a1 a3a3 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

18 Feasibility: TLUT Cone with 3 input nodes that aren’t parameters = TLUT-feasible (3 input LUT) 18 a0a0 I1I1 I2I2 a1a1 a3a3 a2a2 p Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

19 Feasibility: TCON Equivalent to multiplexer controlled by function of parameters = TCON-feasible 19 I1I1 I2I2 p a0a0 a2a2 I2I2 I1I1 p a1a1 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

20 TLC supergate One TLUT with TCONs attached to its inputs 20 TLC TCON TLUT TCON … Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

21 Feasibility: TLC supergate Equivalent to multiplexer controlled by function of parameters and LUTs at its inputs = TLC-feasible 21 p I1I1 I2I2 I3I3 I4I4 q a0a0 a2a2 a1a1 I1I1 I2I2 b0b0 I3I3 I4I4 c1c1 c0c0 pq 0 LUT

22 Feasibility calculation 22 Based on cone function: Ψ a0a0 a2a2 a1a1 I1I1 I2I2 b0b0 I3I3 I4I4 c1c1 c0c0 pq Ψ(I 1,I 2,I 3,I 4,p,q)

23 Feasibility calculation Using Binary Decision Diagram of cone function 23Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 0001111 Ψ

24 Feasibility calculation Using Binary Decision Diagram of cone 24 Ψ f(p,q) k(I 1,I 2,l 4 )m(I 1,I 2,l 3 ) n(I 1,I 3,l 5 ) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

25 Feasibility calculation Using Binary Decision Diagram of cone 25 Ψ f(p,q) s(I 1 )t(I 2 ) v(I 3 ) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

26 EXPERIMENTAL RESULTS 26Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

27 Area and depth 27Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

28 TLC supergate 28Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

29 Execution time and scaling behaviour 29Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

30 Conclusion Automatically map functionality to reconfigurable routing Creates smaller and faster mapping results Part of new toolflow to quickly create specialized configurations 30Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

31 Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt Karel.Heyse@UGent.be 31 FACULTY OF ENGINEERING AND ARCHITECTURE Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

32 Acknowledgement Supported by European Commission FP7 project: The author is supported by a Ph.D. grant of the FWO- Vlaanderen 32Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

33 Toolflow 33 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting Tuneable LUT TLUT g(P) Tuneable Connection TCON LUT Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

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