1. EEE2243 Digital System Design Chapter 5: Simple Design Case Studies by Muhazam Mustapha, February 2011

2. Learning Outcome By the end of this chapter, students are expected to understand a few design case studies –Decoder –Multiplexer –Sequence Generator –Secure Car Key –Flight Attendant Call-Button

3. Chapter Content Decoder Multiplexer Sequence Generator Secure Car Key Flight Attendant Call-Button

4. Decoder

5. A decoder is a combinational circuit that activates its output according to the binary value of its input General block diagram of active high 3-bit decoder: 3-to-8 Decoder I0I0 I1I1 I2I2 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 If I 2 I 1 I 0 = 010, O 2 will be set to HIGH, the rest will be LOW

6. Decoder Most of the decoders available in the market are inverted output (active low): I0I0 I1I1 I2I2 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 If I 2 I 1 I 0 = 010, O 2 will be set to LOW, the rest will be HIGH 3-to-8 Decoder

7. Decoder General truth table and circuit of 2-to-4 active high decoder: I1I1 I0I0 O0O0 O1O1 O2O2 O3O3 001000 010100 100010 110001

8. Decoder Verilog From the definition of decoder it might be obvious now that it easier to write its Verilog code in Boolean algebra rather than behavioral approach module Decoder2to4(codein, codeout); input [1:0] codein; output [3:0] codeout; reg [3:0] codeout; parameter CO0 = 1; // code out 0 parameter CO1 = 2; parameter CO2 = 4; parameter CO3 = 8; always@(codein) begin case (codein) 0: codeout = CO0; 1: codeout = CO1; 2: codeout = CO2; 3: codeout = CO3; endcase end endmodule

9. Multiplexer

10. A multiplexer (mux) is a combinational circuit that transfers its MULTI line inputs to a SINGLE line output according to the binary value of some selector lines General block diagram: S0S0 I0I0 I1I1 I2I2 I3I3 Output I5I5 I6I6 I7I7 If S 2 S 1 S 0 = 010, value at I 2 will be sent to Output 8-to-1 Mux I4I4 S1S1 S2S2

11. Multiplexer General truth table of 8-to-1 multiplexer: S1S1 S0S0 Output 00I0I0 01I1I1 10I2I2 11I3I3

12. Multiplexer Based on the previous truth table, multiplexer can be built using decoder: S1S1 S0S0 I3I3 I2I2 I1I1 I0I0 Decoder Multiplexer Output

13. Multiplexer The simplified circuit: S1S1 S0S0 I3I3 I2I2 I1I1 I0I0 Output

14. Multiplexer Verilog Multiplexer is better be defined in behavioral approach module Mux4to1(sel, lin, lout); input [3:0] lin; input [1:0] sel; output lout; reg [3:0] lout; always@(sel) // latched, lin no effect begin case (sel) 0: lout = lin[0]; 1: lout = lin[1]; 2: lout = lin[2]; 3: lout = lin[3]; endcase end endmodule

15. Secure Car Key Vahid Example 3.4 pg 127

16. Secure Car Key Many new car keys include tiny computer chip –When car starts, car’s computer (under engine hood) requests identifier from key –Key transmits identifier If not, computer shuts off car FSM –Wait until computer requests ID (a=1) –Transmit ID (in this case, 1101) K1K2K3K4 r=1 r=0r=1 Wait r=0 Inputs: a; Outputs: r a’ a Vahid Example 3.4 pg 127

17. Secure Car Key Nice feature of FSM –Can evaluate output behavior for different input sequence –Timing diagrams show states and output values for different input waveforms K1K2K3K4 r=1 r=0r=1 Wait r=0 Inputs: a;Outputs: r a’ a WaitW K1K2K3K4WaitW clk Inputs Outputs State a r clk Inputs a K1 WaitW K1K2K3K4Wait Output State r Q: Determine states and r value for given input waveform: a Vahid Example 3.4 pg 127

18. Flight Attendant Call-Button Vahid Example 3.1 pg 118

19. Flight-Attendant Call Button D flip-flop will store bit Inputs are Call, Cancel, and present value of D flip-flop, Q Truth table shown below Preserve value: if Q=0, make D=0; if Q=1, make D=1 Cancel -- make D=0 Call -- make D=1 Let’s give priority to Call -- make D=1 Circuit derived from truth table, using Chapter 2 combinational logic design process Call button Cancel button Flight attendant call-button system Blue light DQ’ Q Clk Call button Cancel button Blue light Call Cancel Q Vahid Example 3.1 pg 118

20. Verilog Code Write the Verilog code yourself for the cases of Secure Car Key and Flight Attendant Call- Button