0. Digital Principles and Design
PowerPoint Slides
to accompany
Digital Principles and Design
Donald D. Givone
Chapter 5
Logic Design with MSI Components and Programmable Logic Devices

1. Karnaugh maps for the binary full adder.
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Karnaugh maps for the binary full adder.
Figure 5.1
5-1

2. A realization of the binary full adder.
Figure 5.2

3. Parallel (ripple) binary adder.
Figure 5.3

4. Parallel (ripple) binary subtracter.
Figure 5.4

5. Parallel binary subtracter constructed using a parallel binary adder.
Figure 5.5

6. Parallel binary adder/subtracter.
Figure 5.6

7. A carry lookahead adder. (a) General organization. (b) Sigma block.
Figure 5.7   

8. A 4-bit carry lookahead adder.
Figure 5.8

9. Cascade connection of 4-bit carry lookahead adders.
Figure 5.9

10. (a) A carry lookahead generator. (b) a 16-bit high-speed adder.
Figure 5.10                

11. Organization of a single-decade decimal adder.
Figure 5.11

12. Organization of a single-decade BCD adder.
Figure 5.12

13. Karnaugh map to detect the combinations P3P2P1P0 = 1010, 1011, . . . , 1111.
Figure 5.13

14. A single-decade BCD adder.
Figure 5.14

15. Organization of a 1-bit comparator.
Figure 5.15

16. Comparing two binary numbers A and B. (a) 1-bit comparator network
Comparing two binary numbers A and B. (a) 1-bit comparator network. (b) Cascade connection of 1-bit comparators.
Figure 5.16

17. An n-to-2n-line decoder symbol.
Figure 5.17

18. A 3-to-8-line decoder. (a) Logic diagram. (b) Truth table. (c) Symbol.
Figure 5.18

19. Realization of the Boolean expressions f1(x2,x1,x0) = m(1,2,4,5) and f2(x2,x1,x0) = m(1,5,7) with a 3-to-8-line decoder and two or-gates.
Figure 5.19

20. Realization of the Boolean expressions f1(x2,x1,x0) = m(0,1,3,4,5,6) = m(2,7) and f2(x2,x1,x0) = m(1,2,3,4,6) = m(0,5,7) with a 3-to-8-line decoder and two nor-gates.
Figure 5.20

21. A decoder realization of f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.
Figure 5.21

22. A 3-to-8-line decoder using nand-gates. (a) Logic diagram
A 3-to-8-line decoder using nand-gates. (a) Logic diagram. (b) Truth table. (c) Symbol
Figure 5.22

23. Realization of the pair of maxterm canonical expressions f1(x2,x1,x0) = M(0,3,5) and f2(x2,x1,x0) = M(2,3,4) with a 3-to-8-line decoder and two and-gates.
Figure 5.23

24. Realization of the Boolean expressions f1(x2,x1,x0) = M(0,1,3,4,7) = M(2,5,6) and f2(x2,x1,x0) = M(1,2,3,4,5,6) = M(0,7) with a 3-to-8-line decoder and two nand-gates.
Figure 5.24

25. A decoder realization of f1(x2,x1,x0) = m(0,2,6,7) and f2(x2,x1,x0) = m(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.
Figure 5.25

26. And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram
And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
Figure 5.26

27. Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram
Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
Figure 5.27

28. Demultiplexer.
Figure 5.28

29. A 4-to-16-line decoder constructed from 2-to-4-line decoder.
Figure 5.29

30. A 2n-to-n-line encoder symbol.
Figure 5.30

31. An 8-to-3-line encoder.
Figure 5.31

32. A 2n-to-1-line multiplexer symbol.
Figure 5.32

33. A 4-to-1-line multiplexer. (a) Logic diagram (b) Compressed truth table. (c) Symbol.
Figure 5.33

34. A multiplexer tree to form a 16-to-1-line multiplexer.
Figure 5.34

35. A multiplexer/demultiplexer arrangement for information transmission.
Figure 5.35

36. Realization of a three-variable function using a 8-to-1-line multiplexer. (a) Three-variable truth table. (b) General realization.
Figure 5.36

37. Realization of f(x,y,z) = m(0,2,3,5). (a) Truth table
Realization of f(x,y,z) = m(0,2,3,5). (a) Truth table. (b) 8-to-1-line multiplexer realization.
Figure 5.37

38. A general realization of a 3-variable Boolean function using a 4-to-1-line multiplexer.
Figure 5.38

39. Realization of f(x,y,z) = m(0,2,3,5) using a 4-to-1-line multiplexer.
Figure 5.39

40. Obtaining multiplexer realizations using Karnaugh maps
Obtaining multiplexer realizations using Karnaugh maps. (a) Cell groupings corresponding to the data line functions. (b) Karnaugh maps for the Ii subfunctions.
Figure 5.40

41. Realization of f(x,y,z) = m(0,2,3,5). (a) Karnaugh map
Realization of f(x,y,z) = m(0,2,3,5). (a) Karnaugh map. (b) I0, I1, I2, and I3 submaps.
Figure 5.41

42. Using Karnaugh maps to obtain multiplexer realizations under various assignments to the select inputs. (a) Applying input variables y and z to the S1 and S0 select lines. (b) Applying input variables x and y to the S0 and S1 select lines.
Figure 5.42

43. Alternative realizations of f(x,y,z) = m(0,2,3,5)
Alternative realizations of f(x,y,z) = m(0,2,3,5). (a) Applying input variables y and z to the S1 and S0 select lines. (b) Applying input variables x and y to the S0 and S1 select lines.
Figure 5.43

44. A select line assignment and corresponding data line functions for a multiplexer realization of a four-variable function.
Figure 5.44

45. Realizations of f(w,x,y,z) = m(0,1,5,6,7,9,12,15). (a) Karnaugh map
Realizations of f(w,x,y,z) = m(0,1,5,6,7,9,12,15). (a) Karnaugh map. (b) Multiplexer realization.
Figure 5.45

46. Using a four-variable Karnaugh map to obtain a Boolean function realization with a 4-to-1-line multiplexer.
Figure 5.46

47. Realizations of the Boolean function f(w,x,y,z) = m(0,1,5,6,7,9,13,14). (a) Karnaugh map. (b) I0 submap. (c) I1 submap. (d) I2 submap. (e) I3 submap. (f) Realization using a 4-to-1-line multiplexer. (g) Realization using a multiplexer tree.
Figure 5.47

48. General structure of PLDs.
Figure 5.48

49. Buffer/inverter. (a) Symbol. (b) Logic equivalent.
Figure 5.49

50. Programming by blowing fuses. (a) Before programming
Programming by blowing fuses. (a) Before programming. (b) After programming.
Figure 5.50

51. PLD notation. (a) Unprogrammed and-gate. (b) Unprogrammed or-gate
PLD notation. (a) Unprogrammed and-gate. (b) Unprogrammed or-gate. (c) Programmed and-gate realizing the term ac. (d) Programmed or-gate realizing the term a + b. (e) Special notation for an and-gate having all its input fuses intact. (f) Special notiation for an or-gate having all its input fuses intact. (g) And-gate with nonfusible inputs. (h) Or-gate with nonfusible inputs.
Figure 5.51

52. Structure of a PROM.
Figure 5.52

53. A 2n  m PROM. (a) Logic diagram. (b) Representation in PLD notation.
Figure 5.53

54. Using a PROM for logic design. (a) Truth table. (b) PROM realization.
Figure 5.54

55. Logic diagram of an n  p  m PLA.
Figure 5.55

56. Example of combinational logic design using a PLA
Example of combinational logic design using a PLA. (a) Maps showing the multiple-output prime implicants. (b) Partial covering of the f1 and f2 maps. (c) Maps for the multiple-output minimal sum. (d) Realization using a 3  4  2 PLA.
Figure 5.56

57. Example of combinational logic design using a PLA
Example of combinational logic design using a PLA. (a) Maps showing the multiple-output prime implicants. (b) A multiple-output minimal sum covering. (c) Alternative multiple-output minimal sum covering. (d) Realization using a 3  4  2 PLA.
Figure 5.57

58. Exclusive-or-gate with a programmable fuse. (a) Circuit diagram
Exclusive-or-gate with a programmable fuse. (a) Circuit diagram. (b) Symbolic representation.
Figure 5.58

59. General structure of a PLA having true and complemented output capability.
Figure 5.59

60. Karnaugh maps for the functions f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6)
Figure 5.60

61. Two realizations of f1(x,y,z) = m(1,2,3,7) and f2(x,y,z) = m(0,1,2,6). (a) Realization based on f1 and 2 (b) Realization based on 1 and 2 (b) Realization based on 1 and 2 .
Figure 5.61

62. A simple four-input, three-output PAL device.
Figure 5.62

63. An example of using a PAL device to realize two Boolean functions
An example of using a PAL device to realize two Boolean functions. (a) Karnaugh maps. (b) Realization.
Figure 5.63