1. 1 CPC2-CPR2 Assemblies Testing Status Tim Woolliscroft

2. 2 Brief history First signals with assemblies on MB4.2 –Initial test were promising –Failed after one day, unknown cause –All subsequent assemblies in MB4.2 also failed One chip mounted in MB4.4 (from GelPack1) was assumed to be dead GelPack2 inspected –Corrosion found –4 Chips thought to still bondable and good 11/05/07, two more chips mounted onto MB4.4 (#1 & #2) 17/05/07, fault found with MB4.4 (VDC to CPR1 and CPR2 swapped) –First assembly in MB4.4 may have been destroyed unnecessarily 17/05/07, MB4.4 #2 was cooled and Fe55 signals seen Has worked every day this week with overnight shutdown

3. 3 Testing procedure Similar to before except with extreme paranoia 1.Sequencer & CPR Control running 2.Power up the MB ( +/-12V, +/-5V) 3.Power up 3.3V on MB 4.Exercise the opto-couplers on MB (can be ambiguous on power up) 5.Set correct power up mode for CPR 6.Load the DACs on MB -> power CPR with 2.5V 7.Set direct ADC output mode, check for ADC noise 8.Cool 9.Raise the bias of CPR ground and CPC outputs in 2V steps Reverse applies for shutdown, without the warming up bit

4. 4 How it works CPR2 ADCs constantly clocked, output is latched and saved during the CPC clocking. Sequence repeated at 500ms (Fe55 integration time) CPC voltage channels reset after clocking, before upsets the baseline of the CPR ADCs (why?) Time CCD Clock NC MB amplifiers active Reset voltage pulse NC Phase correction for CPR clocks CPR2 ADC digital output is stored to memory CPR2 Voltage amplifier output CPC output Hits ☺ 1MHz CPC clocking

5. 5 How it works CPR2 ADCs constantly clocked, output is latched and saved during the CPC clocking. Sequence repeated at 500ms (Fe55 integration time) CPC voltage channels are reset after clocking, if done before upsets the baseline of the CPR ADCs (why?) Time CCD Clock NC MB amplifiers active Reset voltage pulse NC Phase correction for CPR clocks CPR2 ADC digital output is stored to memory Hit ☺ CPR2 Voltage amplifier output CPC output

6. 6 How it looks Capture Data soon as CPC clock starts, causing a little disruption 300mV ADC Range Baseline is quite flat Hits are clearly visible Disruption at end Select window, linear fit, restore baseline to ADU 32 Noise is around 60 to 100 e- –Need to improve fitting DNL is OK –Few missing codes –But only 1MHz clock and large range

7. 7 Optimisation 3 Timing parameters –CLK1 & 2 duty cycle –CPC–CPR CLK Phase Seems to like Clocks as shown Short CLK2 decreases gain (why?) CPC–CPR CLK Phase not very critical CLK1 CLK2 VOUT2

8. 8 Optimisation 3 Timing parameters –CLK1 & 2 duty cycle –CPC–CPR CLK Phase CPR Biasing ADC range Voltage amp biasing Charge amp biasing Voltage and charge amp offsets

9. 9 Optimisation Variations in clocking and biasing lead to... Amplifier oscillation, Amplifier restoration, overshoot & undershoot

10. 10 Channel Gain Matching Scan all voltage channels, using the same settings. Using 300mV ADC range Plot as signal as 1D histogram Compare edge channel With middle channel Significant drop in gain towards middle of the chip

11. 11 Channel Gain Matching Fe55 Peak Noise Peak Sofa Plot (Gets uncomfortable here) Scan all voltage channels, using the same settings. Using 300mV ADC range Plot as signal as 2D histogram Or as 3D plot Significant drop in gain towards middle of the chip Middle of chip Edge of chip

12. 12 Channel Gain Matching Scan all voltage channels, using the same settings. Using 300mV ADC range Probably not ADC’s, VDC test shows no gain loss ADC 140 ADC 240

13. 13 2MHz Using 200mV ADC Range –Lost a bit in gain –Needs more work to improve gain ADC # 190 85e- noise ADC # 210 65e- noise

14. 14 Conclusions Testing is in the early stages –Voltage channels are working Good noise performance up to 2MHz Still need a little optimisation, difficult to do systematically Gain across the chip is uneven –Nothing but noise from charge channels Seem to be affected by digital signals Possible to get cluster finder working? –Turn of charge channels –Lower hit densities Want to go faster –MB5.0?