1. Robustness of SRAM Memories Universitat Politecnica de Catalunya (UPC) Barcelona Spain Ioana Vatajelu CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

2. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

3. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

4. SRAM bit cell: Minimum size transistors –> high sensitivity to process variability –Inter-die –Intra-die Systematic Random (RDF & LER) asymmetric transistors strengths Parametric Failures Wafer to wafer Die to die Problem Statement CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

5. Problem Statement Pull - up MOSPull - down MOSaccess MOS σ [%]VddW[nm]σ [V]6σ [V]W[nm]σ [V]6σ [V]W[nm]σ [V]6σ [V] 45nm41.1940.0230.1411960.0170.1041130.0230.136 32nm 6 167 0.0350.209 140 0.0260.157 80 0.0350.208 150.0870.5230.0650.3920.0860.519 22nm 8 0.9546 0.0510.306 96 0.0380.229 55 0.0500.302 150.0960.5730.0710.4290.0940.566 300.1911.1470.1430.8570.1891.133 16nm 10 0.933 0.0690.412 70 0.0470.281 40 0.0620.372 200.1370.8230.0940.5620.1240.743 400.2741.6460.1871.1240.2481.487 18nm 33 0.740 0.0670.400 84 0.0460.276 48 0.0610.365 580.1170.7030.0810.4850.1070.642 13nm 39 0.729 0.0790.473 60 0.0550.329 35 0.0720.430 580.1170.7030.0810.4890.1070.640

6. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 00.20.40.60.81 0 0.2 0.4 0.6 0.8 1 00.20.40.60.81 0 0.2 0.4 0.6 0.8 1 00.20.40.60.81 0 0.2 0.4 0.6 0.8 1 Hold Mode Read Mode Write Mode + + V DD GND Problem Statement

7. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Hold ModeRead Mode Write Mode 00.511.5 x 10 -10 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 00.511.5 x 10 -10 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 02468 x 10 -10 -0.2 0 0.2 0.4 0.6 0.8 1 1.2FAIL FAIL FAIL Access FAIL 00.511.5 x 10 -10 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Problem Statement

8. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

9. The SB-SI Method E.I. Vatajelu, J. Figueras, IEEE DATE 2011 min mean Acceptance Region Failure Region

10. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 The SB-SI Method E.I. Vatajelu, J. Figueras, IEEE DATE 2011 Statistical Distribution p1p1 p2p2 p1p1 p2p2

11. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

12. Failure analysis of the 6T SRAM Static analysis - SNM

13. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Failure analysis of the 6T SRAM Static analysis - SNM

14. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

15. Parametric Yield BL BLB NaR NaL PL PR NR NL L R WL‘1’ ‘0’ ΔV TH PL ΔV TH NR ΔV TH NL ΔV TH NR

16. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Parametric Yield

17. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Parametric Yield Hold (P FH ) V DDlow = 0.5V Write (P FW ) T acceess = 1ns Read (P R ) T acceess = 1ns Access (P FA ) T acceess = 1ns Cell (P CELL ) Array (P ARRAY ) 512k Yield (%) 512k PTM 45nm4%01.03e-902.41e-92.87e-91.5e-399.85 32nm 6%9.73e-82.91e-83.34e-87e-81.02e-75.21e-294.79 15%1.01e-74.76e-74.2e-89.32e-77.92e-70.3466.02 22nm 8%1.06e-71.32e-79.47e-81.31e-72.16e-70.10789.29 15%1.56e-63.03e-69.82e-72.66e-65.09e-60.9376.93 30%2.15e-41.49e-47.15e-42.17e-48.23e-410 16nm 10%5.14e-76e-72.91e-73.33e-71.11e-60.44155.88 20%1.93e-52.06e-51.57e-51.8e-53.91e-511.25e-7 40%1.15e-33.33e-39.23e-41.39e-34.76e-310 UoG 18nm 33%9.81e-62.43e-51.06e-51.53e-54.81e-511.11e-9 58%6.3e-31e-24.34e-36.25e-31.42e-210 13nm 39%2.62e-54.19e-52.83e-53.33e-58.32e-511.13e-17 58%4.66e-27.1e-22.04e-25e-21.21e-110 σ [%]Yield (%) 512k PTM 45nm4%99.85 32nm 6%94.79 15%66.02 22nm 8%89.29 15%6.93 30%0 16nm 10%55.88 20%1.25E-07 40%0 UoG 18nm 33%1.11E-09 58%0 13nm 39%1.13E-17 58%0

18. CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Parametric Yield

19. Overview Problem Statement SB-SI Method of Statistical Failure Analysis Failure Analysis of the 6T SRAM cell Parametric Yield of the 6T SRAM memory array Conclusions CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

20. SB – SI Method: – accurate and fast 6T SRAM DRV: – 45nm: DRV = 47%V DDnom ; 16nm: DRV = 75.5%V DDnom 6T SRAM Parametric Yield – @T = 2ns, DRV = 500mV – 45nm: Y = 99.85%, 16nm: Y = 55.88% CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th - 18 th 2011 Conclusions

21. Thanks for your attention! CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011