1. Chapter 3 Internal Memory

2. Objectives  To describe the types of memory used for the main memory  To discuss about errors and error corrections in the memory systems  To discuss more on advanced memory organizations

3. Key points  The two basic forms of semiconductor random access memory are dynamic RAM(DRAM) and static RAM(SRAM). SRAM is faster, expensive, less dense than DRAM and is used for Cache and DRAM is used for main memory.  Error correction techniques are commonly used in memory systems. These involve adding redundant bits that are a function of the data bits to form an error-correcting code. If a bit error occurs, the code will detect and correct the error.  To compensate for the relatively slow speed of DRAM, a number of advanced DRAM organizations have been introduced. The two most common are synchronous DRAM and RamBus DRAM.

4. Semiconductor Memory Types

5. Organization The basic element of a semiconductor memory is the memory cell. All semiconductor memory cells share certain properties:-  They exhibit two stable states, which can be used to represent binary 1 and 0 represent binary 1 and 0  They are capable of being written into, to set the state  They are capable of being read to sense the state.

6. Memory Cell Operation

7. Semiconductor Memory  RAM-random access memory  Misnamed as all semiconductor memory is random access  Read/Write  Volatile-RAM must be provided with constant power supply.  RAM can be used only as Temporary storage  Two traditional forms of RAM used in computers are Static or dynamic(DRAM, SRAM)

8. Dynamic RAM  Bits stored as charge in capacitors and the presence or absence of charge in a capacitor is interpreted as a binary 1 or 0  Because of tendency to discharge, dynamic RAMs require periodic charge refreshing to maintain data storage.  Used as main memory  Simpler construction  Smaller per bit  Less expensive  Need refresh circuits  Slower - need refreshing process  Essentially analogue  Level of charge determines value

9. Dynamic RAM Structure The address line is activated when the bit value from this cell is to be read or written. The transistor acts as a switch that is closed if a voltage is applied to the address line and opened if no voltage present on the address line.

10. DRAM Operation  Write Voltage signals is applied to the bit line; a high voltage represents 1 and low voltage represents 0. A signal is then applied to the address line, allowing a charge to be transferred to the capacitor.  Read when the address line is selected, the transistor turns on and the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier. The sense amplifier compares the capacitor voltage to a reference value and determines if the cell contains a logic 1 or 0. The readout from the cell discharges the capacitor, which must be restored to complete the operation. when the address line is selected, the transistor turns on and the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier. The sense amplifier compares the capacitor voltage to a reference value and determines if the cell contains a logic 1 or 0. The readout from the cell discharges the capacitor, which must be restored to complete the operation.

11. Static RAM  Bits stored as on/off switches  No charges to leak because binary values are stored using traditional flip-flop  No refreshing needed when powered  More complex construction  Larger per bit  More expensive – complex logic gate  Does not need refresh circuits  Faster  Used as Cache memory

12. Stating RAM Structure

13. Static RAM Operation  Transistor arrangement gives stable logic state  State 1  C 1 high, C 2 low  T 1 T 4 off, T 2 T 3 on  State 0  C 2 high, C 1 low  T 2 T 3 off, T 1 T 4 on  Address line transistors T 5 T 6 is switch  Write – apply value to B & compliment to B  Read – value is on line B

14. SRAM v DRAM  Both volatile  Power needed to preserve data  Dynamic cell  Simpler to build, smaller  More dense  Less expensive  Needs refresh  Larger memory units  Static  Faster  Cache

15. Read Only Memory (ROM)  Permanent storage  Nonvolatile  Microprogramming (Stallings Book ch.17)  Library subroutines for frequently wanted functions  Systems programs (BIOS)  Function tables

16. Types of ROM  Written during manufacture  Very expensive for small runs  Programmable (once)  Nonvolatile and may be written into only once  Needs special equipment to program (tools)  Read-mostly memory -> useful for applications in which read operations are far more frequent than write operation  Erasable Programmable (EPROM)  Erased by UV  Electrically Erasable (EEPROM)  Takes much longer to write than read  Flash memory  Erase whole memory electrically

17. Error Correction  Hard Failure  Permanent defect  Soft Error  Random, non-destructive  No permanent damage to memory  Detected using Hamming error correcting code

18. Error Correcting Code Function

19. Advanced DRAM Organization  Basic DRAM same since first RAM chips  Enhanced DRAM  Contains small SRAM as well  SRAM holds last line read  Cache DRAM  Larger SRAM component  Use as cache or serial buffer

20. Synchronous DRAM (SDRAM)  Access is synchronized with an external clock  Address is presented to RAM  RAM finds data (CPU waits in conventional DRAM)  Since SDRAM moves data in time with system clock, CPU knows when data will be ready  CPU does not have to wait, it can do something else  Burst mode allows SDRAM to set up stream of data and fire it out in block  DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

21. SDRAM

22. SDRAM Read Timing

23. RAMBUS  Adopted by Intel for Pentium & Itanium  Main competitor to SDRAM  Vertical package – all pins on one side  Data exchange over 28 wires < cm long  Bus addresses up to 320 RDRAM chips at 1.6Gbps  Asynchronous block protocol  480ns access time  Then 1.6 Gbps

24. RAMBUS Diagram

25. DDR SDRAM  SDRAM can only send data once per clock  Double-data-rate SDRAM can send data twice per clock cycle  Rising edge and falling edge

26. Cache DRAM  Mitsubishi  Integrates small SRAM cache (16 kb) onto generic DRAM chip  Used as true cache  64-bit lines  Effective for ordinary random access  To support serial access of block of data  E.g. refresh bit-mapped screen  CDRAM can prefetch data from DRAM into SRAM buffer  Subsequent accesses solely to SRAM