1. V 0.11 Memory Vocabulary ROM – Read Only Memory - a type of memory that cannot be written, can only be read. Contents determined a manufacture time. –ROM is non-volatile – contents remain even when power is off. PROM – Programmable ROM – a type of memory whose contents can be programmed by the user –OTP – One Time Programmable, a PROM is OTP if contents can be programmed only once. EEPROM – Electrically Erasable PROM – contents be erased electrically by the user. –Memory is not alterable under ‘normal’ operation.

2. V 0.12 Memory Vocabulary RAM – Random Access Memory – memory that can be both read and written during normal operation. –Contents are non-volatile, will be lost on power off. SRAM – static RAM – has the following characteristics: –Read, Write operations take equal amounts of time –Access to any ‘random’ location takes same amount of time. –Fastest access time of memory types. –Basic memory cell is a latch, takes 6 transistors per memory bit.

3. V 0.13 Static Random Access Memory (SRAM) The serial EEPROM had low pin count because of serial I2C interface –Speed was sacrificed –Random access read took 5 bytes (3 bytes to set address, 2 bytes for read). Total of 45 bit times (5 * 9), @400 KHz this took 2.5  s * 45 = 112.5  s! –Write speed was slow because non-volatile memory (page write took about 6.5 ms for 64 bytes, or about 101  s/byte. An SRAM (Static Random Access Memory) has: –equal read/write times, measured in nanoseconds –volatile (contents not maintained when power removed) –equal cycle time, access time –typically has a parallel interface

4. V 0.14 Typical SRAM Control Lines MEMMEM Data[N-1:0] Address[log2(K)-1:0] K x N CS OE W Chip Select – must be asserted before Memory will respond to read or write operation. If negated, data bus is high impedance. OE – Asserted for read operation, Memory will drive data lines. W – Asserted for a write operation (Memory inputs data from data pins, processor writes to memory). Data bus is bidirectional

5. V 0.15 Sense Amps Bit lines (2 per column) Cell Word lines (1 per row) Row Decode Row Address Column Decode Column Address Data lines Bit Line Bias Memory Organization Internal Architecture

6. V 0.16 Static Ram Cell B (bitline)BB (bitline_bar) Wordline

7. V 0.17 Cypress 8K x 8 SRAM Multiple Chip Enables – more flexibility Data bus is bi-directional (8 I/O lines). Note: a more precise name for this memory is Asynchronous SRAM. It has no clock input, any change on address inputs accesses a new location.

8. V 0.18 Read Cycle Cycle Time – how fast can I start another operation? Access Time – how fast is data ready? For SRAMs, Cycle Time = Access Time, this is a feature of SRAMs.

9. V 0.19 Write Cycle

10. V 0.110 Write Timings Notice that Write Cycle = Read Cycle. All volatile RAM types have this feature.

11. V 0.111 PIC To SRAM 8Kx8 IO[7:0] CE2 OE# WE# A[7:0] A[12:8] RA[7:0] RB[4:0] RC[7:0] Vdd CE1# RD0 RD1 To read: Address on RA, RB. RC port is all inputs; RD0 = ‘0’, RD1 = ‘1’. To write: Address on RA, RB. RC port is all outputs; RD0 = ‘1’, RD1 = 0. ‘#’ means low true PIC

12. V 0.112 Expanding Memory 8Kx8 IO[7:0] CE2 OE# WE# A[7:0] A[12:8] RA[7:0] RB[4:0] RC[7:0] CE1# RD0 RD1 8Kx8 IO[7:0] CE2 OE# WE# A[7:0] A[12:8] CE1# RAM1 RAM0 RB5 RAM1 accessed when RB5 = 1 RAM0 accessed when RB5 = 0 PIC

13. V 0.113 More Memory IO[7:0] OE# WE# A[12:0] RA[7:0]RB[4:0], RC[7:0] RD0 RD1 CE1# RAM0 RB[6:5] 13 8 IO[7:0] OE# WE# A[12:0] CE1# RAM1 IO[7:0] OE# WE# A[12:0] CE1# RAM2 IO[7:0] OE# WE# A[12:0] CE1# RAM3 2 0 1 2 3 2-to-4 decoder RB[6:5]=00 RB[6:5]=01 RB[6:5]=10 RB[6:5]=11 chip select decoding PIC

14. V 0.114 Memory Map 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 RB[4:0],RA[7:0]RB[6:5] Total memory = 4 * 8K = 32 K ( 2 5 * 2 10 ), 15 address lines 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Selects chip Selects location within chip 0x0000 low RAM0 0x1FFF high 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x2000 low RAM1 0x3FFF high 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0x4000 low RAM2 0x5FFF high 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x6000 low RAM3 0x7FFF high

15. V 0.115 Other SRAM Types SSRAM - Synchronous SRAM –Has a clock input –Address, data lines latched on clock edge –Can perform burst cycles What is a burst cycle? –After first data value is output based upon address, data values in successive locations are output without needing to change address bus –Internal counter used for address value

16. V 0.116 Synchronous SRAM (SSRAM) Note clock lines to SRAM. A DDR (Double Data Rate) SSRAM means that data is clocked on both clock edges.

17. V 0.117 SSRAM Normal Cycle vs Burst Cycle Address ready, Data ready in clocks. Address ready, 1 st data ready in 2 clocks, successive locations ready in successive clocks. This burst cycle is a 2-1-1-1 cycle. Diagram shows burst suspended for 1 clock between 3 rd & 4 th clock. Normal 2-1-1-1 burst takes 5 clocks.

18. V 0.118 Why Burst Cycles? Burst Cycles more efficient at block memory transfers (memory location is successive locations) –Normal cycle would take 8 clocks to transfer data from 4 locations. –2-1-1-1 burst takes only 5 clocks. Why do we want to transfer blocks of memory efficiently? –For cache fill operations. –So what is a cache?

19. V 0.119 A Cache System CPU Memory (SRAM) Single chip (die) Memory (SSRAM) Processor Module Casing Memory (SSRAM) Main Memory (DRAM) Motherboard 1 st level cache 2 nd level cache 3 rd level cache

20. V 0.120 What is a Cache? The “closer” a memory is to a CPU, the faster the data transfer between CPU and Memory. –Can’t get any closer than on the same chip as the CPU! For high performance microprocessors, need LOTS of memory Don’t have enough room to put all memory on same chip as CPU –Put some memory on same die as CPU, will not be able to hold all needed data/programs but will hold most frequently used data/programs –Will need to swap out some data if we don’t find what we need in the cache (a miss!).

21. V 0.121 Memory Hierarchy Registers Cache Main Memory Fixed Disk Tape Floppy Zip CD-ROM CD-RWR Cost/Bit Access/Speed Capacity The further away, the cheaper per bit. The further away, the slower the access time, the higher the capacity (density).

22. V 0.122 cache and memory account for about 70% of the die. Intel 3 rd Generation IA-64 (executes new 64-bit instructions) 0.13  L1 instr. cache IA-32 CPU (pentium, for compatibility) L2 cache L3 cache

23. V 0.123 Main Memory and DRAM For main memory, we need a memory whose primary characteristics are: –Dense (lots o’ bits!!!) –Cheap (cause we don’t want to spend too much for our lots o’ bits!) –Good at block transfers, can be rotten at random accesses. How do we achieve density? (lots o’ bits?) –Less transistors per bit! Dynamic RAM (DRAM) - one transistor + capacitor per bit!!!!!

24. V 0.124 DRAM Memory Cell Word line Bit line Cs Memory value stored on capacitor ( a very small capacitor...) Turn this transistor on to access data Data value appears on bit line

25. V 0.125 DRAM Characteristics Very dense (high capacity). Cheap per bit. Slow for Random Access (access to any location) –Cycle time >> access time, Read Cycle time = Write cycle time. Has special access modes to speed block transfers –Important since transfers to DRAM in modern computer system is always block-oriented for cache fills. Only has half the address pins that you would expect –1M x 8 DRAM has only 10 address pins instead of 20 –Reduces package size, can pack more DRAM chips per unit area. Address values multiplexed between row/column addresses

26. V 0.126 A 1M x 16 DRAM (Micron Tech.) A0-A9 - 10 address pins DQ1-DQ16 – 16 data pins RAS# - row address strobe – asserted when address pins contain row address. CASL#, CASH# - column address strobe – asserted when address pins contain row address. Both need to be asserted for 16 bit transfers, only one for either high or low byte transfers.

27. V 0.127 Address Muxing Row Address Column Address Assume a 16-bit data wide bus (D0-D15), and 20 address lines A20-A1 (no A0 pin since 16 bit-wide data bus). How are addresses split between Row, Column? A20-A11A10-A1 CPU DRAM controller A20-A1 Decode Chip select DRAM A9-A0 RAS# CASL# CASH# Varies the fastest.

28. V 0.128 DRAM Controllers External logic called a DRAM controller needed to interface to DRAMs. –DRAM interfacing more complex than SRAM Provides muxing of Address lines Assertion of RAS, CAS lines Also keeps DRAM contents refreshed –Capacitors tend to leak. Memory contents needs to continually accessed in order to keep contents valid. –Special ‘refresh’ cycles are supported by DRAMs to support refreshing all of bits in a row with one cycle –DRAM controller responsible for running refresh cycles.

29. V 0.129 RAS asserted first CAS asserted next

30. V 0.130 Block transfer. Access different bits on same row, change column address.

31. V 0.131 Timing Values Random access – Trc = 104ns, Trac = 50 ns (access time from row address strobe assertion) Block Mode –Access time to data on row: 50 ns –To column locations on same row : 25 ns Block transfer much more efficient than random access.

32. V 0.132 DRAM Chip Generations Each time a new DRAM Chip generation is released, capacity goes up by 4x –16K x 1 (late 70’s), 64K x 1, 256K x 1, 1M x 1, 4M x 1, 16M x1, 64M x 1, 256M x 1 (current), 1G x 1 (samples available), 4G x 1 (in labs) –Why? because of muxed addresses, 1 address pin is actually two address bits. Two address bits give 4X more locations.

33. V 0.133 DRAM Modules: SIMMs and DIMMs Mount Memory Device Packages on Circuit Boards to Conserve Space 30-Pin SIMM – First – Single Byte Access Used in “Pairs” Since in x86 1 Word=16 bits 72-Pin SIMM – Four Byte Access Need Pairs for Pentium+ Since 64 bit Data Bus 168-pin DIMM – Eight Byte Access SIMM – Single In-Line Memory Module DIMM – Dual In-Line Memory Module

34. V 0.134 SIMM – Single In-line Memory Module -- 72 pins Capacity varies Picture shows 8M x 32 (32 MByte) SIMMs/DIMMs invented to get denser packaging for DRAMs on motherboards. DRAM Modules

35. V 0.135 Schematic View of 72-Pin SIMM

36. V 0.136 Memory Device Specification “Dimension” of Storage Cell Array – 8 Mb – Refers to Eight Mega-bits (not Mega-Bytes!) 8 Mb (lower case ‘b’ !!) =(8)(1024)(1024)bits =(1)(1024)(1024)Bytes =1MB (upper case ‘B’!!) Single 16Mb Device can be Arranged as: – 16M  1bits – 4M  4nybbles – 2M  8bytes – 1M  16(words in the case of x86) Many Devices are Typically “byte-wide” Devices – N  8

37. V 0.137 DRAM Variations SDRAM – Synchronous DRAM – has clock, supports burst transfers DDR-SDRAM - Double Data Rate SDRAM –Data transferred on EACH clock edge –Double the data rate of SDRAM RDRAM – Rambus DRAM –Will discuss this in more detail later –High speed signaling interface to support very fast data transfers –Very high latency (long access time to first location), but very fast at transferring successive locations – claim is better at block mode transfers than SDRAM/DDR- SDRAM.

38. V 0.138 Dual Port Memories CPU CPU Dual Port Memory (SRAM, SSRAM) Address Data Control Address Data Control Support simulatenous access via two ports (left/right sides). Support simultaneous read accesses to different locations or same locations. Suports simultaneous write accesses to different locations Simultaneous write access to same location is not supported. One obvious application is multiple-processor systems, but useful in many other situations.

39. V 0.139 Flash RAM SRAM-like interface, density of SRAM Non-volatile (retains contents when power is off) Read Cycle time same as SRAM (10’s of nanoseconds) Write Cycle >> Read Cycle –write times in microseconds –Can write individual locations or blocks of locations Applications include smart cards (credit cards, medical history cards, etc) Intel is market leader, has a Flash RAM cell that stores 2-bits per cell (can sense 4 different volage levels from cell).

40. V 0.140 What do you have to know? Differences between SRAM, DRAM in terms of density, speed, functionality Pin functions of a SRAM Memory decoding for SRAM via PIC example Definitions of access time, cycle time for SRAM Difference between Synchronous SRAM, Asynchronous SRAM Dual Port, Flash Memory definitions