1. Digital Logic Design Instructor: Kasım Sinan YILDIRIM
Memory Basics
Digital Logic Design
Instructor: Kasım Sinan YILDIRIM

2. Memory Definitions
Memory A collection of storage cells together with the necessary circuits to transfer information to and from them.
Organized as an indexed array of words.
Word - a typical unit of access for the memory.
Value of the index for each word is the memory address.
Memory Organization ─ the basic architectural structure of a memory in terms of how data is accessed.
Random Access Memory (RAM) ─ a memory organized such that data can be transferred to or from any cell (or collection of cells) in a time that is not dependent upon the particular cell selected.

3. Basic Memory Operations
Data
data written to, or read from, memory
Address
specifies the memory location to operate on
An operation
control information which specifies the type of operation to be performed.
Typical operations are READ and WRITE. CS
Read/Write

4. Basic Memory Operations (continued)
Write Memory ─ an operation that writes a data value to memory:
Place a valid address on the address lines and valid data on the data lines.
Toggle the memory write control line

5. Basic Memory Operations (continued)
Read Memory ─ an operation that reads a data value stored in memory:
Place a valid address on the address lines.
Wait for the read data to become stable.

6. RAM Integrated Circuits
Types of random access memory
Static – information stored in latches
Dynamic – information stored as electrical charges on capacitors
Charge “leaks” off
Periodic refresh of charge required
Dependence on Power Supply
Volatile – loses stored information when power turned off
Non-volatile – retains information when power turned off

7. Static RAM Cell Array of storage cells used to implement static RAM
SR Latch
Select input for control

8. Static RAM Bit Slice 2n 1-bit words Multiple RAM cells Control Lines:
Word select
Bit Select
Data Lines:
Data in
Data out

9. 2n-Word  1-Bit RAM IC Memory arrays can be very large!!!
To build a RAM IC from a RAM slice, we need:
Decoder decodes the n address lines to 2n word select lines
A 3-state buffer
on the data output permits RAM ICs to be combined into a RAM with c  2n words
4-to-16
Word select
Decoder A A 2 3 3 3 1 2
RAM cell A 2 A 2 2 2 3 4 A 1 1 A 1 2 5 6
RAM cel l A A 2 7
16 x 1 8
RAM 9 10
Data
Data 11
input
output 12 13 14
Read/ 15
Write
Memory
RAM cell
enable
(a) Symbol
Read/Write
logic
Data input
Data in
Memory arrays can be very large!!!
Large decoders
Large fanouts for the bit lines
Data
Data out
output
Read/
Bit
Write
select
Read/Write
Chip select
(b) Block diagram

10. Cell Arrays and Coincident Selection
Row decoder
2-to-4
Decoder A 1 3 2
RAM cell
RAM cell
RAM cell
RAM cell 1 2 3 A 2 2 1
Row
RAM cell
RAM cell
RAM cell
RAM cell
select 4 5 6 7
The decoder size and fanouts can be reduced by approximately by using a coincident selection in a 2-dimensional array 2
RAM cell
RAM cell
RAM cell
RAM cell 8 9 10 11 3
RAM cell
RAM cell
RAM cell
RAM cell 12 13 14 15
Read/Write
Read/Write
Read/Write
Read/Write
logic
logic
logic
logic
Data in
Data in
Data in
Data in
Data out
Data out
Data out
Data out
Read/
Bit
Read/
Bit
Read/
Bit
Read/
Bit
Write
select
Write
select
Write
select
Write
select
Data input
Read/Write X X X X
Column select
Data 1 2 3
output
16x1 RAM using 4x4 RAM Cell Array
Column
2-to-4 Decoder
decoder
with enable 2 1 2
Enable A 1 A
Chip select

11. Larger Memories
64K words of 8 bits each
256Kx8 RAM ?

12. Wider Memories
64K words of 8 bits each
64Kx16 RAM?

13. Dynamic RAM (DRAM)
Basic Principle: Storage of information on capacitors.
Charge and discharge of capacitor to change stored value
Use of transistor as “switch” to:
Store charge
Charge or discharge
SRAM cell contains 6 transistors!
3 times cell complexity!
Size??

14. Dynamic RAM - Bit Slice
Sense amplifier is used to change the small voltage change on C into H or L
In the electronics, B, C, and the sense amplifier output are connected to make destructive read into non-destructive read

15. Dynamic RAM - Block Diagram

16. Dynamic RAM Write Timing

17. Dynamic RAM Read Timing

18. DRAM Types