1. Khaled A. Al-Utaibi alutaibi@uoh.edu.sa

2.  Memory Interface and the 3 Buses  Interfacing the 8088 Processor  Interfacing the 8086 Processor  Interfacing the 386 and 486 Processors  Interfacing the Pentium Processor  Address Decoding Techniques

3.  When interfacing memory, all three system buses-the address, control, and data buses-are involved.  The address bus specifies the memory locations to be accessed.  The control bus specifies the direction of the data transfer (into or out of the processor)  The data bus carries the transferred data.

4.  Example 1: Show how to interface a (64K x 8) SRAM chip to an 8088 processor. 8088 Microprocessor 64Kx8 SRAM Interface

5. (1)Because the 8088 has an 8-bit data bus, only a single SRAM chip is required (one memory bank). (2)The memory space of the 8088 processor is 1MB which consists of 1MB/64KB =2 20 /2 16 =2 4 =16 different address ranges each of size 64K as shown in Figure 1. (3)We can map the SRAM chip to any one of these address ranges (say the 14th address range 1110). (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K =2 6 x2 10 = 2 16 ). (5)The address bus of the 8088 (20 address lines A 19 -A 0 ) will be interfaced to the SRAM as follows:  The least significant address lines A 15 -A 0 are used to address memory locations in the SRAM chip as shown in Figure 3.  The most significant address lines A 19 -A 16 are used to select the required address range in the memory space of the 8088 (i.e. select the SRAM chip) as shown in Figure 4. decoding addressing (1)Because the 8088 has an 8-bit data bus, only a single SRAM chip is required (one memory bank). (2)The memory space of the 8088 processor is 1MB which consists of 1MB/64KB =2 20 /2 16 =2 4 =16 different address ranges each of size 64K as shown in Figure 1. (3)We can map the SRAM chip to any one of these address ranges (say the 14th address range 1110). (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K =2 6 x2 10 = 2 16 ). (5)The address bus of the 8088 (20 address lines A 19 -A 0 ) will be interfaced to the SRAM as follows:  The least significant address lines A 15 -A 0 are used to address memory locations in the SRAM chip as shown in Figure 3.  The most significant address lines A 19 -A 16 are used to select the required address range in the memory space of the 8088 (i.e. select the SRAM chip) as shown in Figure 4. decoding addressing A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A9A9 A8A8 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0

6. (6)The control-bus of the 8088 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 3. (7)The data-bus of the 8088 is interfaced to the SRAM by connecting the buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the SRAM as shown in Figure 3. (6)The control-bus of the 8088 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 3. (7)The data-bus of the 8088 is interfaced to the SRAM by connecting the buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the SRAM as shown in Figure 3.

7. Figure 1: Address ranges of the 8088 microprocessor

8. 1011100 0111010 1110101 1101011 Figure 2: Decoding the RD’, WR’ and M/IO’ signals.

9. Figure 3: Memory interface of Example 1.

10. Figure 4: Memory interface of Example 1 with address decoder.

11.  Example 2: Show the decoder required to map the 64K memory interface the previous figure to the address range C0000H to CFFFFH. A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Starting 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Ending 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address decoding addressing

12. Figure 5: Address decoding for Example 2.

13.  Example 3: Show how to interface a (64K x 8) SRAM chip(s) to an 8086 processor. 8086 Microprocessor 64Kx8 SRAM Interface

14. (1)Because the 8086 has a16-bit data bus, two SRAM chips are required (two memory banks 2x64KB = 128KB). (2)The memory space of the 8086 processor is 1MB which consists of 1MB/128 KB = 2 20 / 2 17 = 2 3 = 8 different address ranges each of size 128K as shown in Figure 6. (3)We can map the each one of the two SRAM chips to one of these address ranges (say the 6th address range 111). (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K =2 6 x 2 10 = 2 16 ). (5)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced to the SRAM as follows:  The least significant address lines A 16 -A 1 are used to address memory locations in the SRAM chip as shown in Figure 6.  The most significant address lines A 19 -A 17 are used to select the required address range in the memory space of the 8086 (i.e. select the two SRAM chips) as shown in Figure 6.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both as shown in Table 1. decoding addressing even byte (1)Because the 8086 has a16-bit data bus, two SRAM chips are required (two memory banks 2x64KB = 128KB). (2)The memory space of the 8086 processor is 1MB which consists of 1MB/128 KB = 2 20 / 2 17 = 2 3 = 8 different address ranges each of size 128K as shown in Figure 6. (3)We can map the each one of the two SRAM chips to one of these address ranges (say the 6th address range 111). (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K =2 6 x 2 10 = 2 16 ). (5)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced to the SRAM as follows:  The least significant address lines A 16 -A 1 are used to address memory locations in the SRAM chip as shown in Figure 6.  The most significant address lines A 19 -A 17 are used to select the required address range in the memory space of the 8086 (i.e. select the two SRAM chips) as shown in Figure 6.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both as shown in Table 1. decoding addressing even byte A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A9A9 A8A8 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0

15. (6)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 6. (7)The data-bus of the 8086 is interfaced to the SRAM (See Figure 6) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM. (6)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 6. (7)The data-bus of the 8086 is interfaced to the SRAM (See Figure 6) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM.

16. Figure 5: Address ranges of the 8086 microprocessor

17. Table 1: Selecting the even and odd bytes in the 8086 microprocessor

18. Figure 6: Memory interface of example 3

19.  Example 4: Assume the decoder in previous slide is a three-input NAND gate and determine the range of addresses occupied by this interface.

20.  Example 5: Show how to interface a 64K RAM module to an 8086 processor starting at address C0000H. 8086 Microprocessor 64K RAM Module Interface 64K RAM

21. (1)Because the 8086 has a16-bit data bus, the 64KB RAM module needs to be split into two memory banks each of size 64KB/2 = 32KB). (2)Each memory bank has 32K different memory locations. Hence, it requires 15 address lines (32K =2 5 x 2 10 = 2 15 ). (3)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced to each memory bank as follows:  The least significant address lines A 15 -A 1 are used to address memory locations in memory chip as shown in Figure 7.  The most significant address lines A 19 -A 16 are used to select the memory module starting at address …… as shown in Figure 7.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both as shown in Table 1. decoding addressing even byte (1)Because the 8086 has a16-bit data bus, the 64KB RAM module needs to be split into two memory banks each of size 64KB/2 = 32KB). (2)Each memory bank has 32K different memory locations. Hence, it requires 15 address lines (32K =2 5 x 2 10 = 2 15 ). (3)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced to each memory bank as follows:  The least significant address lines A 15 -A 1 are used to address memory locations in memory chip as shown in Figure 7.  The most significant address lines A 19 -A 16 are used to select the memory module starting at address …… as shown in Figure 7.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both as shown in Table 1. decoding addressing even byte A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A9A9 A8A8 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0 11000000000000000000 11001111111111111111

22. (4)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 7. (5)The data-bus of the 8086 is interfaced to the SRAM (See Figure 7) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM. (4)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 7. (5)The data-bus of the 8086 is interfaced to the SRAM (See Figure 7) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM.

23. A1-A15 A16-A19 A0-A14 32Kx8 A0-A14 Figure 6: Memory interface of example 5

24.  Example 6: Show how to interface a (64K x 8) SRAM chip(s) to a 386/486 processor. 80386 Microprocessor 64Kx8 SRAM Interface

25. (1)Because the 386/486 has a 32-bit data bus, four SRAM chips are required (four memory banks 4x64KB = 256KB). (2)The memory space of the 386/486 processor is 4GB which consists of 4GB/256 KB = 2 32 /2 18 = 2 14 = 16K different address ranges each of size 256K as shown in Figure 7. (3)We can map the each one of the four SRAM chips to one of these address ranges. (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K=2 6 x2 10 =2 16 ). (5)The address bus of the 386/486 (32 address lines) will be interfaced to the SRAM as follows:  The least significant address lines A 17 -A 2 are used to address memory locations in the SRAM chip as shown in Figure 7.  The most significant address lines A 31 -A 18 are used to select the required address range in the memory space of the 386/486 (i.e. select the four SRAM chips) as shown in Figure 7.  The A 0 and A 1 address lines, are not present, instead, the four byte enable signals BE 3 -BE 0 are used to select memory banks. decoding addressing x x (1)Because the 386/486 has a 32-bit data bus, four SRAM chips are required (four memory banks 4x64KB = 256KB). (2)The memory space of the 386/486 processor is 4GB which consists of 4GB/256 KB = 2 32 /2 18 = 2 14 = 16K different address ranges each of size 256K as shown in Figure 7. (3)We can map the each one of the four SRAM chips to one of these address ranges. (4)The SRAM chip has 64K different memory locations. Hence, it requires 16 address lines (64K=2 6 x2 10 =2 16 ). (5)The address bus of the 386/486 (32 address lines) will be interfaced to the SRAM as follows:  The least significant address lines A 17 -A 2 are used to address memory locations in the SRAM chip as shown in Figure 7.  The most significant address lines A 31 -A 18 are used to select the required address range in the memory space of the 386/486 (i.e. select the four SRAM chips) as shown in Figure 7.  The A 0 and A 1 address lines, are not present, instead, the four byte enable signals BE 3 -BE 0 are used to select memory banks. decoding addressing x x A 31 …A 17 A2A2 A1A1 A0A0 A 18 …

26. (6)The control-bus of the 386/486 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 7. (7)The data-bus of the 386/486 is interfaced to the SRAM by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of SRAM-A.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of SRAM-B.  The buffered data lines D 23 -D 16 to input/output lines (I/O 7 -I/O 0 ) of SRAM-C.  The buffered data lines D 31 -D 24 to input/output lines (I/O 7 -I/O 0 ) of SRAM-D. (6)The control-bus of the 386/486 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’) as shown in Figure 2.  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 7. (7)The data-bus of the 386/486 is interfaced to the SRAM by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of SRAM-A.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of SRAM-B.  The buffered data lines D 23 -D 16 to input/output lines (I/O 7 -I/O 0 ) of SRAM-C.  The buffered data lines D 31 -D 24 to input/output lines (I/O 7 -I/O 0 ) of SRAM-D.

27. Figure 7: Memory interface of example 6

28.  Example 7: Describe the decoder required to map the interface in the previous slide to the "bottom" of physical memory (that is, address 00000H). A 31 A 18 A 17 A 2 A 1 A 0 Starting 0000 0000 0000 0000 0000 0000 0000 00XX Address Ending 0000 0000 0000 0011 1111 1111 1111 11XX Address

29. A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Figure 8: Address decoder of example 7

30.  Example 8: Show how to interface a (64K x 8) SRAM chip(s) to a Pentium/Pentium Pro processor. Pentium Microprocessor 64Kx8 SRAM Interface

31. (1)Because the Pentium processors have 64-bit data buses, 8 memory chips (banks) will be required in the interface, providing a total memory capacity of 512K. (2)Like the 386 and 486, byte enable signals (BE 7 -BE0) are provided to select the appropriate chips. (3)The 16 low-order address lines A 3 -A 18 are wired in parallel to each memory chip. (4)The decoder is then required to examine the remaining 13 address lines A 19 -A 31. decoding addressing x x x (1)Because the Pentium processors have 64-bit data buses, 8 memory chips (banks) will be required in the interface, providing a total memory capacity of 512K. (2)Like the 386 and 486, byte enable signals (BE 7 -BE0) are provided to select the appropriate chips. (3)The 16 low-order address lines A 3 -A 18 are wired in parallel to each memory chip. (4)The decoder is then required to examine the remaining 13 address lines A 19 -A 31. decoding addressing x x x A 31 …A 18 A3A3 A2A2 A1A1 A 19 … A0A0

32. Figure 8:Memory interface of example 8

33.  An address decoder is a circuit that examines decoding address lines and enables the memory for a specified range of addresses.  This is an important part of any memory design, as one block of memory must not be allowed to overlap another.  Address decoding techniques can be classified based on two categories: − (1)Type of Decoder Hardware  (a) Logic Gates  (b) Block Decoder  (c) Programmable Array Logic (PAL) Decoder − (2) Size of Address Decoding Lines  (a) Full Address Decoding  (b) Partial Address Decoding

34.  Logic gates such as AND, OR, NOT, NAND, and NOR can be used to implement the function of an address decoder.  For example, a two-input NAND gate recognizes the input pattern 11 and produces an active-low output only when this input combination is applied.  A two-input AND provides a similar function but produces an active-high output indication.  OR and NOR gates can also be used as decoders when their alternate (active-low input) logic symbols are used.  The four possible logic gate decoder combinations are shown in Figure 9.

35. Figure 9: The four possible logic gate decoder combinations

36.  Example 9: Design a decoder for the 8086 SRAM memory interface such that the memory is mapped to the address range 00000-1FFFFH.

37. Figure 10: Address decoders of Example 9

38.  When decoding larger sizes of memory with many memory chips, logic gate decoders become unpractical.  In such cases, block decoders (such as 74LS138 3- to-8 line decoder) are used for memory address decoding.  A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines.  The connection diagram, function table, and logic diagram of the 74LS138 decoder are shown in Figures 11, 12 and 13.

39. Figure 11: Connection diagram of the 74LS13 decoder

40. Figure 12: Function table of the 74LS13 decoder

41. Figure 13: Logic diagram of the 74LS13 decoder

42.  Example 10: Show how to interface a 386 processor to a memory of size 128MB starting at address 0000000H using a 4MBx8 SRAM chips and a block decoder. − (1) Since the 386 requires 4 memory banks, i.e., 4 SRAM chips are needed (1 Module = 4 x 4MB = 16MB). − (2) For a memory of size 128MB, we need to use 128MB/16MB = 8 modules. − (3) We need 22 address lines (4MB = 2 2 x 2 20 = 2 22 ) to address memory location within one SRAM chip. − (4) We need 3 address lines (8 = 2 3 ) to select one memory module out of 8 modules. − (5) We need 5 address lines (4GB/128MB=2 2 x2 30 /2 7 x2 20 = 2 32 /2 27 =25) to enable one memory range out of 32 memory ranges.

43. These four lines select byte, word, or doub1eword (via the four SRAM chips) on each memory module These five lines must be low to enable the required memory range These three lines select one of eight memory modules These 22 lines select one byte within each 4 MB SRAM on each memory module Figure 14: Address partitioning of Example 10

44. Figure 15: Memory interface of Example 10

45.  In this technique, all unused address lines are decoded to generate chip select.  Every unused line has a particular value either 0 or 1.  Each addressable location within the memory components responds to only a single unique address.  All memory system designs seen so far use this type of address decoding.

46.  In this technique, only a subset of unused address lines is used to generate chip select.  The values of un-decoded address bits are considered as don't care for the memory modules.  Thus, each address location may be selected by more than one address combination.  The advantage of this type of address decoding is that it results in reduced hardware for the address decoder.

47.  Example 11: Consider 4 SRAM modules (M0, M1, M2 and M3) each of size 4KB. − Assume that the four modules start at addresses 34000H, 36000H, 3C000H and 3F000H respectively. − Show how to interface these four memory modules to an 8086 microprocessor using the following address decoding methods:  (a) Full decoding using NAND gates.  (b) Partial decoding using NAND gates.  (c) Full decoding using a decoder.  (d) Partial decoding using a decoder.

48. (1)Because the 8086 has a16-bit data bus, each 4KB module needs to be split into 2 memory banks each of size 4KB/2 = 2KB. (2)Each memory bank has 2K different memory locations. Hence, it requires 11 address lines (2K =2 1 x 2 10 = 2 11 ). (3)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced as follows:  The least significant address lines A 11 -A 1 are used to address memory locations in each memory chip.  The most significant address lines A 19 -A 12 are used to select the memory modules.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both. (1)Because the 8086 has a16-bit data bus, each 4KB module needs to be split into 2 memory banks each of size 4KB/2 = 2KB. (2)Each memory bank has 2K different memory locations. Hence, it requires 11 address lines (2K =2 1 x 2 10 = 2 11 ). (3)The address bus of the 8086 (20 address lines A 19 -A 0 ) will be interfaced as follows:  The least significant address lines A 11 -A 1 are used to address memory locations in each memory chip.  The most significant address lines A 19 -A 12 are used to select the memory modules.  The address line A 0 and BHE’ signal are used to select even byte, odd byte or both.

49. (4)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’).  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 16. (5)The data-bus of the 8086 is interfaced to the SRAM (See Figure 16) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM. (4)The control-bus of the 8086 is interfaced to the SRAM as follows:  Decode the M/IO’, RD’, and WR’ signals to generate 4 signals Memory Read (MEMR’), Memory Write (MEMW’), I/O Read (IOR’) and I/O Write (IOW’).  Connect MEMR’ to OE’ and MEMW’ to WE’ as shown in Figure 16. (5)The data-bus of the 8086 is interfaced to the SRAM (See Figure 16) by connecting:  The buffered data lines D 7 -D 0 to input/output lines (I/O 7 -I/O 0 ) of the even SRAM.  The buffered data lines D 15 -D 8 to input/output lines (I/O 7 -I/O 0 ) of the odd SRAM. All steps described above are common for the four types of address decoding requested in Example 10 (a-d). These decoding technique differ in the design of the address decoder shown as a box labeled “Decoder” in Figure 16. The details of the four address decoding techniques will be shown in the next slides. All steps described above are common for the four types of address decoding requested in Example 10 (a-d). These decoding technique differ in the design of the address decoder shown as a box labeled “Decoder” in Figure 16. The details of the four address decoding techniques will be shown in the next slides.

50. A1-A11 A12-A19 A0-A12 2Kx8 A0-A12 Figure 16: Memory interface of example 11

51. Full Decoding Using NAND Gates:

52. Partial Decoding Using NAND Gates: (1)Ignore common address lines (A 19 -A 16, A 14 ). (2)Use the minimum number of remaining address lines (A 15, A 13, A 12 ) as inputs to the NAND gates (3)Since A 15 and A 13 are enough to distinguish the three modules, these two address lines are used with the NAND gates. Partial Decoding Using NAND Gates: (1)Ignore common address lines (A 19 -A 16, A 14 ). (2)Use the minimum number of remaining address lines (A 15, A 13, A 12 ) as inputs to the NAND gates (3)Since A 15 and A 13 are enough to distinguish the three modules, these two address lines are used with the NAND gates. common bits

53. Full Decoding Using a Decoder: (1)Use common address lines (A 19 -A 16, A 14 ) to enable the decoder. (2)Use the remaining address lines (A 15, A 13, A 12 ) as input to the decoder (3)Since 3 address lines are used as inputs to the decoder, we need a 3x8 decoder. (4)Connect memory select lines to the proper outputs of the decoder. Full Decoding Using a Decoder: (1)Use common address lines (A 19 -A 16, A 14 ) to enable the decoder. (2)Use the remaining address lines (A 15, A 13, A 12 ) as input to the decoder (3)Since 3 address lines are used as inputs to the decoder, we need a 3x8 decoder. (4)Connect memory select lines to the proper outputs of the decoder. common bits

54. Partial Decoding Using a Decoder: (1)Ignore common address lines (A 19 -A 16, A 14 ). (2)Use the minimum number of remaining address lines (A 15, A 13, A 12 ) as input to the decoder. (3)Since A 15 and A 13 are enough to distinguish the three modules, these two address lines are used as inputs to the decoder. (4)Since 2 address lines are used as inputs to the decoder, we need a 2x4 decoder. (5)Connect memory select lines to the proper outputs of the decoder. Partial Decoding Using a Decoder: (1)Ignore common address lines (A 19 -A 16, A 14 ). (2)Use the minimum number of remaining address lines (A 15, A 13, A 12 ) as input to the decoder. (3)Since A 15 and A 13 are enough to distinguish the three modules, these two address lines are used as inputs to the decoder. (4)Since 2 address lines are used as inputs to the decoder, we need a 2x4 decoder. (5)Connect memory select lines to the proper outputs of the decoder. common bits