2. Integrated Circuits Costs
IC cost = Die cost Testing cost Packaging cost
Final test yield
Die cost = Wafer cost
Dies per Wafer * Die yield
Dies per wafer = š * ( Wafer_diam / 2)2 – š * Wafer_diam – Test dies
Die Area ¦ 2 * Die Area
Die Yield = Wafer yield * 1 +

Defects_per_unit_area * Die_Area  { }
Die Cost goes roughly with die area4

3. Real World Examples
Chip Metal Line Wafer Defect Area Dies/ Yield Die Cost layers width cost /cm2 mm2 wafer
386DX $ % $4
486DX $ % $12
PowerPC $ % $53
HP PA $ % $73
DEC Alpha $ % $149
SuperSPARC $ % $272
Pentium $ % $417
From "Estimating IC Manufacturing Costs,” by Linley Gwennap, Microprocessor Report, August 2, 1993, p. 15

4. Learning Curve “When volume doubles, cost reduces 10%”
Gordon Bell 1978
Example: PCs v. Workstations
PC 24M 33M M 65M
WS .41M M M .98M
Ratio
65x ~ 2^6 --> .9^6 = 0.53

5. Pipelining: Its Natural!
Laundry Example
Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold
Washer takes 30 minutes
Dryer takes 40 minutes
“Folder” takes 20 minutes A B C D

6. Sequential Laundry Sequential laundry takes 6 hours for 4 loads
6 PM 7 8 9 10 11
Midnight
Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k O r d e A B C D
Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?

7. Pipelined Laundry Start work ASAP
6 PM 7 8 9 10 11
Midnight
Time 30 40 20 T a s k O r d e A B C D
Pipelined laundry takes 3.5 hours for 4 loads

8. Pipelining Lessons
6 PM
Pipelining doesn’t help latency of single task, it helps throughput of entire workload
Pipeline rate limited by slowest pipeline stage
Multiple tasks operating simultaneously
Potential speedup = Number pipe stages
Unbalanced lengths of pipe stages reduces speedup
Time to “fill” pipeline and time to “drain” it reduces speedup 7 8 9
Time T a s k O r d e 30 40 20 A B C D

9. Computer Pipelines
Execute billions of instructions, so throughout is what matters
DLX desirable features: all instructions same length, registers located in same place in instruction format, memory operands only in loads or stores

10. Example: MIPS (­ DLX) Register-Register Op Rs1 Rs2 Rd Opx31 26 25 21 20 16 15 11 10 6 5 Op
Rs1
Rs2 Rd
Opx
Register-Immediate 31 26 25 21 20 16 15
immediate Op
Rs1 Rd
Branch 31 26 25 21 20 16 15
immediate Op
Rs1
Rs2/Opx
Jump / Call 31 26 25
target Op

11. 5 Steps of DLX Datapath Figure 3.1, Page 130
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
Memory
Access
Write
Back IR L M D

12. Pipelined DLX Datapath Figure 3.4, page 137
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc.
Write
Back
Memory
Access
Data stationary control
local decode for each instruction phase / pipeline stage

13. Visualizing Pipelining Figure 3.3, Page 133
Time (clock cycles) I n s t r. O r d e

14. Its Not That Easy for Computers
Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle
Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away)
Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)
Control hazards: Pipelining of branches & other instructionsstall the pipeline until the hazardbubbles” in the pipeline