1. DP/MP System Architectures
Dezső Sima
Fall 2008
(Ver. 1.0)
 Sima Dezső, 2008

2. Contents 1. The evolution of Intel’s basic microarchitectures
2. Intel’s DP servers
3. Intel’s MP servers
4. AMD’s servers

3. 1. The evolution of Intel’s basic microarchitectures

4. 1. The evolution of Intel’s basic microarchitectures (1)
Figure: Intel’s Tick-Tock development model [22]

5. 1. The evolution of Intel’s basic microarchitectures (2)
Figure: The speed of changes in Intel’s Tick-Tock development model [24]

6. 1. The evolution of Intel’s basic microarchitectures (3)
Wide dynamic execution
- 4-wide decode/rename/retire
Advanced digital media processing
- 128-bit wide SSE execution unit
Improved graphics/MM
- New SSE 4.1 instructions
Smart memory access
- Memory disambiguation (spec. loads)
-Hardware prefetching
Advanced smart cache
- Low latency, high BW shared L2 cache
Figure: Key enhancements introduced into the Core2 microarchitecture (vs the Pentium4) [22]

7. 1. The evolution of Intel’s basic microarchitectures (4)
Figure: Key enhancements introduced into the Penryn microarchitecture (vs the Core) [23]

8. 1. The evolution of Intel’s basic microarchitectures (5)
Figure: Improvements introduced into the Nehalem microarchitecture (vs Penryn) [22]

9. 1. The evolution of Intel’s basic microarchitectures (6)
Figure: Hyperthreading in
the Nehalem microarchitecture [22]

10. 1. The evolution of Intel’s basic microarchitectures (7)
2-level cache hierarchy
3-level cache hierarchy
Figure: 3-level cache hierarchy of Nehalem [22]

11. 1. The evolution of Intel’s basic microarchitectures (8)
Figure: Nehalem’s innovations in the system architecture [22]

12. 1. The evolution of Intel’s basic microarchitectures (9)
Figure: Nehalem’s innovations in the system architecture [22]

13. 1. The evolution of Intel’s basic microarchitectures (10)
QickPath Interconnect
Formerly: Common System interconnect (CSI)
3.2 GHz DDR
20-bit (16-bit data 4-bit CRC) on each lane
12.8 GT/s on each direction
Fastest FSB
400 MHz QDR 8 Byte
12.8 GT/s bidirectional
HyperTransport Bus
Typical speed and width figures in AMD’s systems
HT 1.0: 0.8 GHz DDR 2-Byte
3.2 GT/s on each direction
HT 2.0: 1.0 GHz DDR 2-Byte
4.0 GT/s on each direction
HT 3.0: 2.6 GHz DDR 2-Byte
10.4 GT/s on each direction

14. 2. Intel’s DP Servers

15. 2. Intel’s DP servers (1) P4 P4
Prestonia
Prestonia
PCI-X v.2.2
FSB
400/533 MHz
(1-2 slots)
HI 2.0
1066
GbE
E7500/E7501
1600-
2128
SDRAM
8/12/16 GB
GbE c.
SDRAM
PCI-X
HI 2.0
interface
DDR 200/266
bridge
1066
MCH
SATA c.
registered, ECC opt.
SATA
1600-
2128
SDRAM
HI 2.0
SDRAM
1066
interface
SCSI
SCSI c.
(with RASUM)
PCI-X v.2.2
HI 1.5
266
(1-2 slots)
PCI v.2.2
SVGA
Video c.
133
LAN
MbE
Ultra ATA/100
MbE c.
2*100
(2 ports)
PCI v.2.2
ICH3-S
(3 slots)
GPIO
USB v. 1.1
1.5
(5 ports) ~5
LPC
FWH
SIO FD KB MS SP PP
Figure: Typical configuration of an early DP-server motherboard
based on Intel’s E7500/E7501 (Plunas) chipset

16. based on Intel’s E7520 (Lindenhurst) chipset
2. Intel’s DP servers (2) P4 P4
Nocona
Paxville DP
Nocona
Paxville DP
FSB
800 MHz
3200
PCI-X v.1.0b
PCI E. x8
4000
2128-
3200
SDRAM
16/24/32 GB
GbE
GbE c.
E7520
SDRAM
PCI-X
PCI E. x8
interface
DDR 266/333, DDR2 400
bridge
4000
MCH
registered, ECC opt.
SCSI
SCSI c.
2128-
3200
SDRAM
PCI E. x8
SDRAM
4000
interface
PCI-X v.1.0b
(with RASUM)
PCI E. x8
(or 2x x4)
HI 1.5
266
PCI v.2.3
SVGA
Video c.
133
Ultra ATA/100
2*100
(2 ports)
LAN
MbE
MbE c.
SATA
PCI v.2.3
ICH5R
2*150
(2 ports)
USB v. 2.0 60
(4 ports)
GPIO
AC' 97 v.2.3
~1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure: Typical configuration of an advanced early DP-server motherboard
based on Intel’s E7520 (Lindenhurst) chipset

17. 2. Intel’s DP servers (3)
Paxville DP 2.8
2xIrwindale cores/90 nm
Figure: Intel’s Pentium 4 based DC DP server processors [33], [34]

18. Figure: Genealogy of the Xeon Paxville core
2. Intel’s DP servers (4)
Intel’s first 64-bit Xeon
Nocona
Irwindale
Nocona
Paxville
(L2 enlarged to 2MB)
(2 x Irwindale cores)
(DP enhanced Prescott)
(DP enhanced Prescott 2M)
6/2004
90 nm
112 mm2
125 mtrs
mPGA 604
2/2005
90 nm
135 mm2
169 mtrs
mPGA 604
10/2005
90 nm
2 x 135 mm2
2 x 169 mtrs
Xeon DP 2.8
Xeon MP
mPGA 604
In contrast: corresponding
desktop processors have
the LGA 775 socket.
Figure: Genealogy of the Xeon Paxville core
Sources:

19. (65 nm shrink of the Irwindale)
2. Intel’s DP servers (5)
Xeon 5000
(Dempsey)
Paxville DP 2.8
2xIrwindale cores/90 nm
2xCedar Mill/65 nm
(65 nm shrink of the Irwindale)
Figure: Intel’s Pentium 4 based DC DP server processors [33], [34]

20. 2. Intel’s DP servers (6)
Xeon 5100
(Woodcrest)
Xeon 5300
(Clowertown)
Core2-based/65 nm
Core2-based/65 nm
2xXeon 5100
Figure: Intel’s Core2 based DC/QC DP server processors [33], [35], [36]

21. 2. Intel’s DP servers (7)
Xeon 5400
(Harpertown)
Figure: Intel’s Penryn based QC DP server processor/45 nm (Source: Intel)

22. 2. Intel’s DP servers (8)
Figure: Contrasting the die shots of the Xeon 5400 and 5300 processors [24]

23. 2. Intel’s DP servers (9) Table: Intel’s DC, QC DP servers Series
--- (Paxville DP)
5000 (Dempsey)
5100 (Woodcrest)
5200 (Wolfdale)
5300 (Clovertown)
5400 (Harpertown)
Dual/Quad-Core DC QC
Models
Xeon DP 2.8
E5205/E5260/ X5275
E /X5355
E5405-E5472, X5450-X5482
Microarchitecture
Pentium 4
Core2
Penryn
Core
2*Irwindale dies
2*Cedar dies
Single die
2*Woodcrest dies
2*Penryn
Intro.
10/2005
5/2006
6/2006
11/2007
11/2006
Techology
90 nm
65 nm
45 nm
Die size
2*135 mm2
2*81 mm2
143 mm2
2*143 mm2
2*107 mm2
Nr. of transistors
2*169 mtrs
2*188 mtrs
291 mtrs
2*291 mtrs
2*410 mtrs
Fc [GHz]
2.8 L2
2*2 MB
4 MB
6 MB
2*4 MB
2*6 MB
FSB [MT/s]
800
667/1066
1066/1333
1333/1600
TDP [W]
135
95/130
65/80
80/120
80/120/150
Socket
PGA 604
LGA 771
LGA771
EM64T  HT
--- ED VT
EIST
 (5140 or above)
La Grande
AMT2
Flex Migration
Table: Intel’s DC, QC DP servers

24. 2. Intel’s DP servers (10)
Gainstown
???
(Q1/2009)
(Q1/2010?)
Nehalem-based/45 nm
Westmere_based/32 nm
(Socket 1366)
Figure: Intel’s future DP server processors [21]
(Both 2-way multithreaded)

25. 2. Intel’s DP servers (11)
DP Platforms
10/2005
DP Cores
Xeon DP 2.8 DC
/Paxville DP) DC
90 nm/2*169 mtrs
2*2 MB L2
800 MT/s
PGA604
6/2004
DP Chipsets
7520
(Lindenhurst)
800 MT/s
2 x DDR/DDR2
16 GB
Pentium4-based (90/65 nm)
Figure : Intel’s late Pentium4 based and subsequent DP server platforms

26. 2. Intel’s DP servers (12) Single
Nocona
Paxville DC
SC/DC
Nocona
Paxville
SC/DC
Single
800MT/s
6.4 GB/s
7520
(Lindenhurst)
24 Lanes
PCIe
7.5GB/s
Dual DDR2
400 MT/s
6.4 GB/s
Figure: Evolution of Intel’s DP servers

27. based on Intel’s E7520 (Lindenhurst) chipset
2. Intel’s DP servers (13) P4 P4
Nocona
Paxville DP
Nocona
Paxville DP
FSB
800 MHz
3200
PCI-X v.1.0b
PCI E. x8
4000
2128-
3200
SDRAM
16/24/32 GB
GbE
GbE c.
E7520
SDRAM
PCI-X
PCI E. x8
interface
DDR 266/333, DDR2 400
bridge
4000
MCH
registered, ECC opt.
SCSI
SCSI c.
2128-
3200
SDRAM
PCI E. x8
SDRAM
4000
interface
PCI-X v.1.0b
(with RASUM)
PCI E. x8
(or 2x x4)
HI 1.5
266
PCI v.2.3
SVGA
Video c.
133
Ultra ATA/100
2*100
(2 ports)
LAN
MbE
MbE c.
SATA
PCI v.2.3
ICH5R
2*150
(2 ports)
USB v. 2.0 60
(4 ports)
GPIO
AC' 97 v.2.3
~1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure: Typical configuration of an advanced early DP-server motherboard
based on Intel’s E7520 (Lindenhurst) chipset

28. Pentium4/Core2-based (65 nm)
2. Intel’s DP servers (11)
06/2006
DP Platforms
5000
(Bensley)
10/2005
5/2006
6/2006
11/2006
DP Cores
Xeon DP 2.8 DC
Xeon 5000
Xeon 5100
Xeon 5300
/Paxville DP) DC
(Dempsey) DC
(Woodcrest) DC
(Clowertown) QC
90 nm/2*169 mtrs
2*2 MB L2
800 MT/s
PGA604
65 nm/2*188 mtrs
2*2 MB L2
667/1066 MT/s
LGA771
65 nm/291 mtrs
4 MB L2
667/1066 MT/s
LGA771
65 nm/2*291 mtrs
2*4 MB L2
667/1066 MT/s
LGA771
6/2004
6/2006
DP Chipsets
7520
5000P
5000V/Z
(Lindenhurst)
(Blackford)
(Blackford V/Z)
2xFSB
1066MT/s
800 MT/s
2 x DDR/DDR2
16 GB
4 x FBDIMM
(DDR2)
64GB
2 x FBDIMM
(DDR2)
16GB
Pentium4-based (90/65 nm)
Pentium4/Core2-based (65 nm)
Figure : Intel’s late Pentium4 based and subsequent DP server platforms

29. 2. Intel’s DP servers (14) Single
Dempsey
Woodcrest
Clowertown DC
Dempsey
Woodcrest
Clowertown DC
Nocona
Paxville
SC/DC
Nocona
Paxville
SC/DC
Single
Dual
1066MT/s
17.1 GB/s
800MT/s
6.4 GB/s
7520
(Lindenhurst)
5000
(Blackford)
24 Lanes
PCIe
7.5GB/s
24 Lanes
PCIe
7.5GB/s
Dual DDR2
400 MT/s
6.4 GB/s
Quad FB-DIMM
533 MT/s
17.1 GB/s
Figure: Evolution of Intel’s DP servers

30. 2. Intel’s DP servers (15)
Intel’s Bensley platform [30]
(Actually the block diagram of Tyan’s S5370 DP server)

31. 2. Intel’s DP servers (16)
FB-DIMM
DDR2
Xeon DC/QC
5000 DC
5100 DC
5300 QC
64 GB
5000P
SBE2
Figure: Bensley DP motherboard, with the 5000 (Blackford) chipset
(Supermicro X7DB8+) for the Xeon 5000 DC/QC DP processor families [7]

32. 2. Intel’s DP servers (17)
Table: Latency and bandwidth scaling of the Intel 5000 platform (2006)
vs the earlier generation (2004) [1]

33. Pentium4/Core2-based (65 nm)
2. Intel’s DP servers (11)
06/2006
10/2007
DP Platforms
5000
5100
(Bensley)
(Cranberry Lake)
10/2005
5/2006
6/2006
11/2006
11/2007
DP Cores
Xeon DP 2.8 DC
Xeon 5000
Xeon 5100
Xeon 5300
Xeon 5200
Xeon 5400
/Paxville DP) DC
(Dempsey) DC
(Woodcrest) DC
(Clowertown) QC
(Harpertown) DC
(Harpertown) QC
90 nm/2*169 mtrs
2*2 MB L2
800 MT/s
PGA604
65 nm/2*188 mtrs
2*2 MB L2
667/1066 MT/s
LGA771
65 nm/291 mtrs
4 MB L2
667/1066 MT/s
LGA771
65 nm/2*291 mtrs
2*4 MB L2
667/1066 MT/s
LGA771
45 nm/850 mtrs
2*6 MB L2
1066/1333 MT/s
LGA771
45 nm/850 mtrs
2*6 MB L2
1066/1333 MT/s
LGA771
6/2004
6/2006
10/2007
DP Chipsets
7520
5000P
5000V/Z
5100
(Lindenhurst)
(Blackford)
(Blackford V/Z)
(San Clemente)
2xFSB
1066MT/s
800 MT/s
2 x DDR/DDR2
16 GB
2xFSB
1333/1066 MT/s
2 x DDR2
32/48 GB
4 x FBDIMM
(DDR2)
64GB
2 x FBDIMM
(DDR2)
16GB
Pentium4-based (90/65 nm)
Pentium4/Core2-based (65 nm)
Penryn-based (45 nm)
Figure : Intel’s late Pentium4 based and subsequent DP server platforms

34. 2. Intel’s DP servers (18) Figure: The Cranberry Lake platform [19]
Xeon 5400 (QC)
Xeon 5200 (DC)
5100 chipset
Figure: The Cranberry Lake platform [19]

35. QuickPath Interconnect
2. Intel’s DP servers (19)
Integrated
memory controller
QuickPath Interconnect
Figure: Intel’s forthcoming Nehalem-based DP server system architecture [31]

36. 3. Intel’s MP servers

37. 3. Intel’s MP servers (1)
Potomac
Paxville MP
Tulsa
90 nm
65 nm
65 nm
Figure: Intel’s Pentium4 based Xeon MP processors [17], [18]
CDM: Cedar Mill core

38. 3. Intel’s MP servers (2) Figure: Intel’s Core2 /Penryn based
45 nm
Figure: Intel’s Core2 /Penryn based
Xeon MP processors [19], [20]
Core2 based
65 nm

39. Cedar Mill-based single die
3. Intel’s MP servers (3)
Series
7000 (Paxville MP)
7100 (Tulsa)
7200 (Tigerton DC)
7300 (Tigerton QC)
7400 (Dunnington QC)
7400 (Dunnington 6C)
Dual/Quad-Core DC
2xSC
2xDC QC 6C
Models
7110M-7140M / 7110N-7150N
E7210/E7220
E7310/E7320/E7330/E7340/X7350
E7420-E7440
E7450/X7460
Microarchitecture
Netburst
Core 2
Penryn
Core
2xIrwindale dies
Cedar Mill-based single die
2xSC Woodcrest dies
2xWoodcrest dies
Intro.
11/2005
8/2006
9/2007
9/2008
Techology
90 nm
65 nm
45 nm
Die size
2*135 mm2
435 mm2
2*143 mm2
503 mm2
Nr. of transistors
2*169 mtrs
1328 mtrs
2*291 mtrs
1900 mtrs
Fc [GHz]
2.4/2.93
1.6/2.13/2.4/2.4/2.93
2.40/2.66 L2
2*1/2 MB1
2*1 MB
2*4 MB
2*2/2*2/2*3/2*4/2*4 MB
3*2 MB
3*3 MB L3
---
4/8/16 MB
8/12/16 MB
12/16 MB
FSB [MT/s]
667/800
1066
TDP [W]
95/150 80
80/80/80/80/130 90
90/130
Socket
mPGA604
mPGA 604
EM64T  HT ED VT
EIST
La Grande
n.a.
AMT2
 (Except E7310)
1 Concerning the L2 cache size, there is a contradiction in Intel’s dokumentation; whereas according to the data sheets models of the 7000 series include 1 or 2 MB L2 caches the comparison charts for all models shows 1 MB large L2 caches.
Table: Dual- and Quad-Core Xeon MP-lines

40. 3. Intel’s MP servers (4)
Figure: Intel’s Nehalem based MP server processor [21]

41. 3. Intel’s MP servers (5)
Xeon MP1
Xeon MP1
Xeon MP1
Xeon MP1 SC SC SC SC
Preceding NBs
Typically HI 1.5
(266 MB/s)
1 Xeon MP before Potomac
Figure: Evolution of Intel’s Xeon MP-based system architecture (until the appearance of Nehalem)

42. 3. Intel’s MP servers (6)
Figure: Former Pentium II/III MP systemarchitecture [32]

43. Figure : Intel’s Xeon-based MP server platforms
3. Intel’s MP servers (7)
3/2005
MP Platforms
Truland
Truland
3/2005
11/2005
8/2006
MP Cores
Xeon MP
Xeon 7000
Xeon 7100
(Potomac SC)
(Paxville MP DC)
(Tulsa DC)
90 nm/675 mtrs
1 MB L2
8/4 MB L3
667 MT/s
mPGA 604
90 nm/2x169 mtrs
2x1 (2) MB L2 -
800/667 MT/s
mPGA 604
65 nm/1328 mtrs
2x1 MB L2
16/8/4 MB L3
800/667 MT/s
mPGA 604
3/2005
4/2006
MP Chipsets
8500
8501
(Twin Castle)
(?)
2xFSB
667 MT/s
4 x XMB
(2 x DDR2)
32GB
2xFSB
800 MT/s
4 x XMB
(2 x DDR2)
32GB
P4-based/90 nm
P4-based/65 nm
Figure : Intel’s Xeon-based MP server platforms

44. 3. Intel’s MP servers (8)
Truland
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Xeon MP1
Xeon MP1
Xeon MP1
Xeon MP1 SC SC SC SC
DC/SC
DC/SC
DC/SC
DC/SC
Preceding NBs
(Twin Castle)
XMB
8500
XMB
XMB
XMB
Typically HI 1.5
28 PCIe lanes + HI 1.5
(266 MB/s)
Caneland
(7 GT/s)
(266 MT/s)
1 Xeon MP before Potomac
Figure: Evolution of Intel’s Xeon MP-based system architecture (until the appearance of Nehalem)

45. 3. Intel’s MP servers (9) Serial link (North Bridge)
Xeon DC MP 7000
(4/2005) or later
DC/QC MP 7000 processors
Independent
Memory
Interface
Serial link
5.33 GB inbound BW
2.67 GB outbound BW
simultaneously
(North Bridge)
eXxternal
Memory
Bridge
Intelligent MC
Dual mem. channels
DDR 266/333/400
4 DIMM/channel
Figure: Intel’s 8501 chipset for MP servers (4/ 2006) [4]

46. for the Xeon 7000/7100 DC MP processor families [7]
3. Intel’s MP servers (10)
FB-DIMM
DDR2
Xeon DC
7000/7100
64 GB
E8501 NB
ICH5R SB
Figure: Quad socket Intel E8501 chipset based motherboard (Supermicro X6QT8)
for the Xeon 7000/7100 DC MP processor families [7]

47. 3. Intel’s MP servers (11)
Figure Bandwith bottlenecks in Intel’s 8501 MP server platform [2]

48. Figure : Intel’s Xeon-based MP server platforms
3. Intel’s MP servers (12)
3/2005
9/2007
MP Platforms
Truland
Truland
Caneland
Caneland
3/2005
11/2005
8/2006
9/2007
9/2008
MP Cores
Xeon MP
Xeon 7000
Xeon 7100
Xeon 7200
Xeon 7300
Xeon 7400
(Potomac SC)
(Paxville MP DC)
(Tulsa DC)
(Tigerton DC)
(Tigerton) QC
(Dunnington 6C)
90 nm/675 mtrs
1 MB L2
8/4 MB L3
667 MT/s
mPGA 604
90 nm/2x169 mtrs
2x1 (2) MB L2 -
800/667 MT/s
mPGA 604
65 nm/1328 mtrs
2x1 MB L2
16/8/4 MB L3
800/667 MT/s
mPGA 604
65 nm/2x291 mtrs
2x4 MB L2 -
1066 MT/s
mPGA 604
65 nm/2x291 mtrs
2x(4/3/2) MB L2 -
1066 MT/s
mPGA 604
45 nm/1900 mtrs
9/6 MB L2
16/12/8 MB L3
1066 MT/s
mPGA 604
3/2005
4/2006
9/2007
MP Chipsets
8500
8501
7300
7300
(Twin Castle)
(?)
(Clarksboro)
2xFSB
667 MT/s
4 x XMB
(2 x DDR2)
32GB
2xFSB
800 MT/s
4 x XMB
(2 x DDR2)
32GB
4xFSB
1066 MT/s
4 x FBDIMM
(DDR2)
512GB
P4-based/90 nm
P4-based/65 nm
Core2-based/65 nm
Core2-based/45 nm
Figure : Intel’s Xeon-based MP server platforms

49. 3. Intel’s MP servers (13)
Truland
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Potomac2
Paxville MP3
Xeon MP1
Xeon MP1
Xeon MP1
Xeon MP1 SC SC SC SC
DC/SC
DC/SC
DC/SC
DC/SC
Preceding NBs
(Twin Castle)
XMB
8500
XMB
XMB
XMB
Typically HI 1.5
28 PCIe lanes + HI 1.5
(266 MB/s)
Caneland
(7 GT/s)
(266 MT/s)
Tigerton
Tigerton
Tigerton
Tigerton
Dunnington
Dunnington
Dunnington
Dunnington
6C/QC/DC
6C/QC/DC
6C/QC/DC
6C/QC/DC
(Clarksboro)
7300
FB-DIMM
(DDR2)
2 First x86-64 MP processor
Cransfield SC)
Tulsa (DC)
3 Supports also
1 Xeon MP before Potomac
8 PCI-E lanes + ESI
(2 GT/s)
(1 GT/s)
Figure: Evolution of Intel’s Xeon MP-based system architecture (until the appearance of Nehalem)

50. for the Xeon 7200/7300 DC/QC MP families (9/2007) [6]
3. Intel’s MP servers (14)
Xeon
7200 (Tigerton DC, Core2), DC
7300 (Tigerton QC, Core2), QC
FB-DIMM
up to 512 GB
Figure: Intel’s four socket 7300 (Caneland) platform, based on the 7300 (Clarksboro) chipset
for the Xeon 7200/7300 DC/QC MP families (9/2007) [6]

51. for the Xeon 7200/7300 DC/QC MP processor families [7]
3. Intel’s MP servers (15)
FB-DIMM
DDR2
192 GB
Xeon
7200 DC
7300 QC
(Tigerton)
ATI ES1000 Graphics with     32MB video memory
7300 NB
SBE2 SB
Figure: Caneland MP motherboard, with the 7300 (Clarksboro) chipset (Supermicro X7QC3)
for the Xeon 7200/7300 DC/QC MP processor families [7]

52. vs the Bensley platform with a dual core Xeon 7140M [13]
3. Intel’s MP servers (16)
Figure: Performance comparison of the Caneland platform with a quad core Xeon (7300 family)
vs the Bensley platform with a dual core Xeon 7140M [13]

53. 3. Intel’s MP servers (17)
QPI
FB-DIMM
(DDR2)
Figure: Intel’s Nehalem based MP server system architecture [22]

54. 4. AMD’s servers

55. System Request Interface
4. AMD’s servers (1)
UP: Opteron 100/1000, DP: Opteron 200/2000
MP: Opteron 800/8000
CPU0
1MB
L2 Cache
CPU1
System Request Interface
Crossbar Switch
Memory
Controller HT 1 2
HyperTransport™
2 x 72 bit
800/8000: 3 coherent links
200/2000: 1 coherent link
Figure: Basic structure of the Opteron families [8]

56. 4. AMD’s servers (2)
AMD’s 4P/8P Direct Connect server architecture [2]

57. 4. AMD’s servers (3)
Figure: Block diagram of a DP QC motherboard (Asus KFSN4-DRE/SAS)
for AMD Opteron 2300 QC family [10]

58. 4. AMD’s servers (4)
nForce 2200 chipset
DDR2
64 GB
Opteron QC DP
2300
Figure: DP motherboard (Asus KFSN4-DRE/SAS) for the AMD Opteron 2300 QC family [10]

59. 4. AMD’s servers (5)
Figure: Block diagram of a QP QC motherboard (ASUS KFN5-Q/SAS)
for AMD’s Opteron 8000 DC/QC familes [10]

60. 4. AMD’s servers (6)
Opteron QC MP
8300
DDR2
64 GB
nForce
3600 chipset
Figure: 4-socket motherboard (ASUS KFN5-Q/SAS) for the AMD Opteron 8000 DC/QC familes [10]

61. 4. AMD’s servers (7)
Figure: Simplified block diagram of the QC Barcelona [25]

62. 4. AMD’s servers (8)
Figure: Die shot and floor plan of Barcelona [27]

63. 4. AMD’s servers (9)
Barcelona (65 nm)
Shanghai (65 nm)
Figure: Cache architectures of AMD’s QC Barcelona and Shanghai processors [25], [26]

64. 4. AMD’s servers (10) Figure: Die shot of Shanghai [29] 6 MB shared L3
Pin to pin
compatible
with Barcelona
Figure: Die shot of Shanghai [29]

65. 4. AMD’s servers (11)
(Virtualisation)
Figure: AMD’s roadmap for DP/MP platforms (2000/8000 Series) [28]

66. Literature (1) References
[1]: Radhakrisnan S., Sundaram C. and Cheng K., „The Blackford Northbridge Chipset for the Intel 5000,”
IEEE Micro, March/April 2007, pp
[2]: Next-Generation AMD Opteron Processor with Direct Connect Architecture – 4P Server Comparison
_PID_41461.pdf
[3]: Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) – Datasheet,
Sept
[4]: Intel® E8501 Chipset North Bridge (NB) Datasheet, Mai 2006,
[5]: Conway P & Hughes B., „The AMD Opteron Northbridge Architecture”, IEEE
MICRO, March/April 2007, pp
[6]: Intel® 7300 Chipset Memory Controller Hub (MCH) – Datasheet, Sept. 2007,
[7]: Supermicro Motherboards,
[8] Sander B., „AMD Microprocessor Technologies,” 2006,
[9]: AMD Quad FX Platform with Dual Socket Direct Connect (DSDC) Architecture ,
[10]: Asustek motherboards -

67. Literature (2)
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Aug. 2005,
[12] Kanter, D. „A Preview of Intel's Bensley Platform (Part II),” Real Word Technologies,
Nov. 2005,
[13] Quad-Core Intel® Xeon® Processor 7300 Series Product Brief, Intel, Nov. 2007
[14] „AMD Shows Off More Quad-Core Server Processors Benchmark” X-bit labs, Nov. 2007
[15] AMD, Nov
[16]: Rusu S., “A Dual-Core Multi-Threaded Xeon Processor with 16 MB L3 Cache,” Intel, 2006,
[17]: Goto H., Intel Processors, PCWatch, March ,
[18]: Gilbert J. D., Hunt S., Gunadi D., Srinivas G., “The Tulsa Processor,” Hot Chips 18, 2006,
[19]:Goto H., IDF 2007 Spring, PC Watch, April ,

68. Literature (3)
[20]: Hruska J., “Details slip on upcoming Intel Dunnington six-core processor,” Ars technica,
February 26, 2008,
upcoming-intel-dunnington-six-core-processor.html
[21]: Goto H,, 32 nm Westmere arrives in , PC Watch, March ,
[22]: Singhal R., “Next Generation Intel Microarchitecture (Nehalem) Family:
Architecture Insight and Power Management , IDF Taipeh, Oct. 2008,
-Taipei_TPTS001_100.pdf
[23]: Smith S. L., “45 nm Product Press Briefing,”, IDF Fall 2007,
ftp://download.intel.com/pressroom/kits/events/idffall_2007/BriefingSmith45nm.pdf
[24]: Bryant D., “Intel Hitting on All Cylinders,” UBS Conf., Nov. 2007,
aa5a-0c46e8a1a76d/UBSConfNov2007Bryant.pdf
[25]: Barcelona's Innovative Architecture Is Driven by a New Shared Cache ,
[26]: Larger L3 cache in Shanghai, Nov , AMD,
[27]: Shimpi A. L., “Barcelona Architecture: AMD on the Counterattack,” March ,
Anandtech,

69. [30]: 2-way Intel Dempsey/Woodcrest CPU Bensley Server Platform, Tyan,
Literature (4)
[28]: Rivas M., “Roadmap update,”, 2007 Financial Analyst Day, Dec. 2007, AMD,
[29]: Scansen D., “Under the Hood: AMD’s Shanghai marks move to 45 nm node,”
EE Times, Nov ,
[30]: 2-way Intel Dempsey/Woodcrest CPU Bensley Server Platform, Tyan,
[31]: Gelsinger P. P., “Intel Architecture Press Briefing,”, 17. March 2008,
[32]: Mueller S., Soper M. E., Sosinsky B., Server Chipsets, Jun 12, 2006,
[33]: Goto H., IDF, Aug ,
[34]: TechChannel,
fk=432919&id=il
[35]: Intel quadcore Xeon 5300 review, Nov , Hardware.Info,
5300_review

70. [36]: Wasson S., Intel's Woodcrest processor previewed, The Bensley server platform debuts,
Mai 23, 2006, The Tech Report,