1. Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2010 Memory Overview

2. Today Memory –Motivation –Organization –Basic components –Optimization concerns Penn ESE370 Fall2010 -- DeHon 2

3. Know how to store state Penn ESE370 Fall2010 -- DeHon 3

4. Register Storage Could just put together a large number of registers Penn ESE370 Fall2010 -- DeHon 4

5. Concerns? Large number of wires –Could determine area Not able to update all on every cycle Not able to use all on every cycle May want to store for many cycles Penn ESE370 Fall2010 -- DeHon 5

6. Limited Data Use What if can only use one on each cycle? –Use with shared data path Need to select the one output –Can only update one Need to control which one gets written Penn ESE370 Fall2010 -- DeHon 6

7. Limited Data Use Add load enable to register Logic to enable one on write Mux to select output Penn ESE370 Fall2010 -- DeHon 7

8. Good Solution? Could get away with just latch –Not full register with master/slave latch Pay large amount for decode and mux –Proportional to memory bits Penn ESE370 Fall2010 -- DeHon 8

9. Memory Idea Maximize storage density (bits/cm 2 ) By minimizing the size/complexity of the repeated element Use shared periphery circuits to provide full functionality Trades off bandwidth (concurrent access) to save area Penn ESE370 Fall2010 -- DeHon 9

10. Memory Bank Penn ESE370 Fall2010 -- DeHon 10

11. Share Address Decode Words – group of bits read/written together –All have same control Penn ESE370 Fall2010 -- DeHon 11

12. Share Address Decode Words Mux select bits (words) from row read Penn ESE370 Fall2010 -- DeHon 12

13. Share Address Decode Result: only spend N 0.5 area (perimeter) on selecting rather than linear in bits Penn ESE370 Fall2010 -- DeHon 13

14. Memory Row Use shared enable for wire economy –Word line Penn ESE370 Fall2010 -- DeHon 14

15. Memory Column Use shared bus for area and wire economy –Row enable selects the cells to read/write from bus Penn ESE370 Fall2010 -- DeHon 15

16. Memory Cell Hold data Conditionally drive onto output bus Conditionally overwritten with data from bus Penn ESE370 Fall2010 -- DeHon 16

17. Penn ESE534 Spring2010 -- DeHon 17 SRAM Memory bit

18. Penn ESE534 Spring2010 -- DeHon 18 SRAM Memory bit Core is back-to-back inverters for storage –Like static latch

19. Penn ESE534 Spring2010 -- DeHon 19 SRAM Memory bit Core is back-to-back inverters for storage –Like static latch –Doesn’t include disable to minimize size

20. Penn ESE534 Spring2010 -- DeHon 20 SRAM Memory bit Pass gate mux for output to column –Bit-Line (BL)

21. Penn ESE534 Spring2010 -- DeHon 21 SRAM Memory bit How do we write into this cell? –No directionality to pass gate –If drive BL strong enough, can flip value in selected cell Ratioed operation

22. Column Capacitance What is capacitance of bit line (column)? –W access (M5,M6) – transistor width of column device –d rows –  =C diff /C gate Penn ESE370 Fall2010 -- DeHon 22

23. Time Driving Bit Line In terms of W access, W buf (M1,M3), d For W access =W buf =4, d=1024,  =0.5 Penn ESE370 Fall2010 -- DeHon 23

24. Column Capacitance Consequence Want W access, W buf small to keep memory cell small Increasing W access, also increases C bl –Don’t really win by sizing up Driving bit line will be slow Penn ESE370 Fall2010 -- DeHon 24

25. Column Sensing Speedup read time by sensing limited swing Sense circuit detects small change in bit line voltage(s) –Precharge to intermediate voltage –BL and /BL swing opposite directions Amplifies for output Penn ESE370 Fall2010 -- DeHon 25

26. Output Amps Bottom of array includes Sense Amplifiers from bit lines to output Penn ESE370 Fall2010 -- DeHon 26

27. Column Write Writes driven from outside array Use large driver –Strong enough to flip memory bit –Strong so can charge column quickly Disable when not write –Be careful on your project2 –Could overwrite wrong row Penn ESE370 Fall2010 -- DeHon 27

28. Complete Memory Bank Penn ESE370 Fall2010 -- DeHon 28

29. Admin Project 2 out –Due November 17 Note recommend milestones Time change this weekend (Sunday 2am) –Extra hour to work on project? Next week normal –Lectures MWF –Office hours Penn ESE370 Fall2010 -- DeHon 29

30. Idea Memory for compact state storage Share circuitry across many bits –Minimize area per bit  maximize density Aggressively use: –Pass transistors, Ratioing –Precharge, Amplifiers to keep area down Penn ESE370 Fall2010 -- DeHon 30