1. Interrupts By Ryan Morris

2. Overview ● I/O Paradigm ● Synchronization ● Polling ● Control and Status Registers ● Interrupt Driven I/O ● Importance of Interrupts

3. I/O Paradigm ● All I/O devices connect to a bus ● Processor Accesses I/O through fetch/store – All I/O devices are assigned a bus address

4. Synchronization ● Problems: – Devices cannot remember a list of commands, circuits execute commands as they are given – Processors are much faster than I/O devices, therefor the CPU must wait for one instruction to be executed before issuing the following command

5. Polling ● Most common way for older software to instruct the processor handle I/O devices. – CD/DVD, Keyboard, Mouse, Printer, etc. ● In essence the processor repeatedly asks devices if they are ready for the next instruction.

6. How to use polling ● Polling uses Fetch portion of fetch-store paradigm ● Because I/O uses a bus for access, pointers can be used to reference the memory area for a specific I/O device. On x86 System, memory address 0xb8000 is the start of the video ram. This address begins in the upper left corner, the following code will print “Hi” on the screen if compiled and linked as an x86 bootsector: void _start() {... } int main() { char *video = (char *) 0xb8000; video[0] = “H”; video[1] = 0x7; video[2] = “i”; video[3] = 0x7; while(1); }

7. How to use polling ● The following example demonstrates how to use polling via fetch-store to determine if a device is ready. Suppose the on a particular device on a fictitious machine which requires bus addresses 0x120000- 0x130000, the address 0x120000 is 0 when the device is busy and non-zero when it is available. The address 0x130000 causes the device to perform some arbitrary function when set to 1. The following code would issue a command to the device, then wait for it to become available, then execute the command again. void test() { int *exec; int *wait; exec = 0x130000; wait = 0x120000; *exec = 1; while(*wait != 0); *exec = 1; }

8. Control and Status Registers ● Control Register – contiguous set of addresses that respond to store operation ● Status Register – contiguous set of addresses that respond to fetch operation

9. Main disadvantages of polling ● Requires lots of while() loops ● While circuits are non-complex and cheap, they are substantially slower than modern CPUs ● Adversely effect the systems performance

10. Interrupt Driven I/O ● Main differences: – Device tells CPU when it is done – Allows hardware to run independently of system – Requires 2-way bus to inform CPU upon completion of operation – Processors are required to have a method to stop current process to handle device – Different methods of programming (Polling vs Interrupt)

11. How interrupts work ● They don't actually “interrupt” anything ● They are simply realized between the execution of two instructions in the CPU's fetch-execute cycle. Repeat Forever { Test: any device interrupts? Fetch: access next step at IP Execute: perform next instruction }

12. Interrupt vector ● Essential for the interrupt process ● Each device is assigned a unique number in an array. These numbers act as an index to a pointer to the code in memory for that device. ● When an interrupt is triggered, the CPU asks which device activated the interrupt, the device responds with its unique number and the processor accesses that code in memory.

13. Interrupts ● When a computer starts up, generally interrupts are not checked for by the CPU until the OS turns interrupts on. ● Further more, most architectures disable interrupts while handling others.

14. Interrupt priority ● Problems can arise when a device that does not need to be serviced immediately, but takes a long time to service, interrupts the same time a device which needs service immediately. ● Processors usually have 7-15 levels of priority – This assures that hard drives get read/written before a printer head is moved.

15. Interrupt Priority ● Manual Assignment – User configures both hardware and software to the correct interrupt priority ● Automatic Assignment – Computer starts, CPU uses bus to automatically assign priority.

16. Direct Memory Access ● Important aspect of high speed I/O ● Allows I/O devices to transfer data directly into memory without the intervention of the CPU – Allows the CPU to keep processing without having to read from the I/O device and then write to memory

17. Buffer Chaining ● Allows data coming from I/O devices to be stored in memory as a link list so it can be dealt with when the CPU is ready. ● Directly derived from DMA

18. Buffer Chaining ● Scatter Read – dividing large block of incoming data into multiple small buffers ● Gather Write – combining data from multiple small buffers into a single output block

19. Operation Chaining ● Generally a linked list in memory containing nodes with an operation and operand(s) ● The devices uses DMA to access the linked list and carries out the specified command with the operands provided, without the involvement of the CPU.

20. Importance of Interrupts ● Allows the processor to be free of controlling devices directly ● Allows for DMA and high speed I/O ● Opened doors for USB

21. Conclusion ● I/O Paradigm ● Synchronization ● Polling ● Control and Status Registers ● Interrupt Driven I/O ● Importance of Interrupts

22. Questions? ● Any Questions?