1. A Light-Weight C/C++ Based Tool for Hardware Verification Alexander Kamkin kamkin@ispras.ru CTestBench Institute for System Programming of the Russian Academy of Sciences http://hardware.ispras.ru

2. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20102 of 2 4 Variety of tools for hardware verification Simulation-based verification  Methods and approaches Co-simulation, CRV, ABV, CDV, etc  Languages and tools SystemC, SystemVerilog, CTESK, etc Formal methods-based verification  Methods and approaches Model checking, automated theorem proving, etc  Languages and tools SMV, SPIN, HOL, PVS, etc

3. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20103 of 2 4 Verification engineer’s professional skills Programming skills  Languages (C/C++, Perl, Shell, etc)  Tools (compilers, debuggers, IDEs, etc) Hardware verification skills  Languages (SystemVerilog, OpenVera, PSL, etc)  Methods (AVM, OVM, UniTESK, etc) Hardware design skills  Languages (Verilog, VHDL, SystemC, etc)  Simulators (ModelSim, VCS, etc), PLI (VPI, DPI, etc) Mathematical background  Discrete mathematics, mathematical logic, etc

4. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20104 of 2 4 “As simple as possible but not simpler” Shortening a VE’s learning curve  Simple and clear conception of a method  Minimum of constructs in a tool’s core  Well-known programming languages  Well-known development environments Extending the tool facilities by easy integration  FSM-based test generators  Test parallelization mechanisms  Web-based test management system  Specialized libraries for test generation

5. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20105 of 2 4 Why C/C++? Easy learning  Ideal for teaching young specialists  All verification engineers know C/C++ Integration with simulators and tools  VPI (Verilog Procedural Interface)  DPI (Direct Programming Interface) Code reuse  Golden (reference) models in a verification environment  Modules of a cross-development simulation environment Efficiency  Shortening test execution time  Shortening simulation time

6. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20106 of 2 4 CTestBench architecture Core Modeling core Testing core Libraries External tools Test generation tools Report generation tools Test management tools Components Generators Examples

7. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20107 of 2 4 CTestBench modeling core Model void cycle() void reset() Interface void start() void stop() Message void getField() void setField() MyInterface void start() void stop() MyMessage void getField() void setField() MyModel void operation 1 () void operation 2 () extends uses

8. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20108 of 2 4 CTestBench operation description void MyModel::MyOperation(Process &process, Interface &iface, Message &message) { start();// Starting the operation // Setting input signals for(...) {...// Performing some action cycle();// Emulating a cycle check(...);// Checking some condition } stop();// Stopping the operation }

9. East-West Design and Test Symposium, St. Petersburg, September 17-20, 20109 of 2 4 CTestBench testing core Test void run() void start() void delay() MyMediator void read() void write() void sync() MyTest void run() extends contains MyModel void operation 1 () void operation 2 ()

10. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201010 of 2 4 CTestBench test case void MyTest::run() { start(); for(...) { Message msg1, msg2;... // Starting two operations in parallel start(MyOperation1, model.iface1, msg1); start(MyOperation2, model.iface2, msg2); // Emulating 10 cycles delay(10); } stop(); }

11. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201011 of 2 4 Synchronization with an RTL model MyMediator void read() void write() void sync() extends MyModel void operation 1 () void operation 2 () read write sync

12. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201012 of 2 4 Testbench development process Development of a reference model  Interfaces, operations, data types, etc Debugging of a reference model  Simple test cases Synchronization with an RTL model  Synchronization functions Development of a test generators  Complex test cases

13. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201013 of 2 4 Beyond the core FSM-based test generators Constraint-driven randomization Verilog code analyzers Test parallelization engine Test management system Report generators

14. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201014 of 2 4 Experience Translation lookaside buffer CTESK Floating point unit CTESK L2 cache CTESK Commutator CTESK Interrupt controller CTESK / CTestBench Memory access unit CTESK / CTestBench

15. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201015 of 2 4 Contacts Institute for System Programming of RAS (ISPRAS) http://www.ispras.ru http://www.ispras.ru Hardware verification R&D @ ISPRAS http://hardware.ispras.ru http://hardware.ispras.ru Alexander Kamkin kamkin@ispras.ru

16. East-West Design and Test Symposium, St. Petersburg, September 17-20, 201016 of 2 4 Thank You! Questions?