1. Real Intent, Inc. 2008 (1) Copyright © 2005 - Real Intent Real Intent, Inc. EnVision Suite of EDA Solutions

2. Real Intent, Inc. 2008 (2) Copyright © 2005 - Real Intent Real Intent Corporate Company founded 1999 World Wide Offices Worldwide headquarters and R&D - Sunnyvale, CA Development Centers - Austin,TX; Portland, OR; Boston, MA CTC - Japanese Distributor Black Forest - European Distributor Maojet – Taiwanese Distributor

3. Real Intent, Inc. 2008 (3) Copyright © 2005 - Real Intent Real Intent Customers

4. Real Intent, Inc. 2008 (4) Copyright © 2005 - Real Intent What is EnVision?  A suite of advanced verification tools  Designed to enhance existing verification flows  Easy to deploy through support of standards  Interoperate with major simulators  Based on proven formal technology  Newly architected for performance  Patented formal algorithms  Increase design quality at lowest cost

5. Real Intent, Inc. 2008 (5) Copyright © 2005 - Real Intent EnVision in your flow Ascent™ Automatic Formal Conquest™ Advanced Verification Meridian CDC™ Verification PureTime™ Exception Verification Early Functional Verification Timing Closure Verification EnVision TCVEnVision EFV

6. Real Intent, Inc. 2008 (6) Copyright © 2005 - Real Intent Ascent Improving Early Design Quality Ascent is a unique automatic formal verification solution  Quickly finds design errors without testbenches  Completely automatic  Comprehensive formal checking  Unique hierarchical reporting – low noise  Supports PSL / SVA constraints  System Verilog Support AUTOMATICASSERTIONS Dead code  Uninitialized Memory  Constant RTL expressions  Constant nets  Constant state vector bits  Unreachable FSM states  Single FSM deadlock  Pairwise FSM deadlock  Bus contention  Floating buses  Full-case pragma violations  Parallel-case pragma violations  X value propagation  Array bounds violations 

7. Real Intent, Inc. 2008 (7) Copyright © 2005 - Real Intent Conquest Static Formal ABV Industry’s easiest formal solution  Static formal ABV tool  Replace and run from simulation script Comprehensive language support  Mixed Verilog, VHDL, SV Powerful debug  Precise diagnosis info for failures  Assertion trace visualization RTL Source & Assertions Convergence Formal Engine Extend Processing ResultResult VerifiedVerified Proof IncompleteProofCounterexample(Bug)

8. Real Intent, Inc. 2008 (8) Copyright © 2005 - Real Intent Meridian Multi-Strategy CDC Verification Verifies clock domain crossing behavior Fastest time to first result  Ease and automation of setup Completeness of analysis / templates  All synchronizer types & FIFOs  Gray code analysis  Both function and structure Best debug and reporting  Quick isolation of root cause error  Minimization of signoff burden

9. Real Intent, Inc. 2008 (9) Copyright © 2005 - Real Intent PureTime Timing Exception Verification Fast exception consistency analysis  Report important exception errors Full sequential verification  False & Multicycle path verification  Glitch and interaction aware Easy setup, easy to run  Design + SDC file + environment file Smart reporting  VCD traces help debug failed exceptions