1. Introduction to Computer Organization and Architecture Lecture 3 By Juthawut Chantharamalee http://dusithost.dusit.ac.th/~jutha wut_cha/home.htm

2. Outline HDL Overview Why not use “C”?  Concurrency  Hardware datatypes / Signal resolution  Connectivity / Hierarchy  Hardware simulation SystemVerilog Introduction Datapaths and Control Paths Moore and Mealy State Machines Examples State Encoding 2Introduction to Computer Organization and Architecture

3. HDL Overview Hardware Description Languages  Used to model digital systems  Can model anything from a simple gate to a complete system  Support design hierarchy  Support Hardware Design Methodology Can model “real” hardware (synthesizable) Can model behavior (e.g. for test) Most widely used are VHDL and VerilogHDL  Both are non-proprietary, IEEE standards Behavioral and structural coding styles 3Introduction to Computer Organization and Architecture

4. 4 Basic Design Methodology SimulateRTL Model Gate-level Model Synthesize SimulateTest Bench ASIC or FPGA Place & Route Timing Model Simulate Requirements Device Libraries

5. Why Not Use C or C++? HDLs need to support characteristics of “real” hardware  Concurrency  Hardware datatypes / Signal resolution  Connectivity / Hierarchy  Circuit timing HDLs must support hardware simulation  Time  Cycle-accurate or Event-driven (for simulation speed) Note: C++ has been extended for hardware  SystemC Introduction to Computer Organization and Architecture5

6. Basic Comparison Verilog  Similar to C  Popular in commercial, on coasts of US  Designs contained in “module”s VHDL  Similar to Ada  Popular in Military, midwest US  Designs contained in “entity” “architecture” pairs Introduction to Computer Organization and Architecture6

7. Concurrency  HDLs must support concurrency Real hardware has many circuits running at the same time!  Two basics problems Describing concurrent systems Executing (simulating) concurrent systems Introduction to Computer Organization and Architecture7

8. Describing Concurrency  Many ways to create concurrent circuits initial/always (Verilog) and process (VHDL) blocks Continuous/concurrent assignment statements Component instantiation of other modules or entity/architectures  These blocks/statements execute in parallel in every VHDL/Verilog design Introduction to Computer Organization and Architecture8

9. Executing Concurrency  Simulations are done on a host computer executing instructions sequentially  Solution is to use time-sharing Each process or always or initial block gets the simulation engine, in turn, one at a time  Similar to time-sharing on a multi-tasking OS, with one major difference There is no limit on the amount of time a given process gets the simulation engine Runs until process requests to give it up (e.g. “wait”) Introduction to Computer Organization and Architecture9

10. Process Rules  If the process has a sensitivity list, the process is assumed to have an implicit “wait” statement as the last statement Execution will continue (later) at the first statement  A process with a sensitivity list must not contain an explicit wait statement Introduction to Computer Organization and Architecture10

11. Sensitivity List With Explicit List XYZ_Lbl: process (S1, S2) begin S1 <= ‘1’; S2 <= ‘0’ after 10 ns; end process XYZ_Lbl; Without Explicit List XYZ_Lbl: process begin S1 <= ‘1’; S2 <= ‘0’ after 10 ns; wait on S1, S2; end process XYZ_Lbl; Introduction to Computer Organization and Architecture11

12. Incomplete Sensitivity Lists Logic simulators use sensitivity lists to know when to execute a process  Perfectly happy not to execute proc2 when “c” changes  Not simulating a 3-input AND gate though! What does the synthesizer create? Introduction to Computer Organization and Architecture12 -- complete proc1: process (a, b, c) begin x <= a and b and c; end process; -- incomplete proc2: process (a, b) begin x <= a and b and c; end process;

13. Datatypes  Verilog has two groups of data types Net Type – physical connection between structural elements  Value is determined from the value of its drivers, such as a continuous assignment or a gate output  wire/tri, wor/trior, wand/triand, trireg/tri1/tri0, supply0, supply1 Variable (Register) Type – represents an abstract data storage element  Assigned a value in an always or initial statement, value is saved from one assignment to the next  reg, integer, time, real, realtime Introduction to Computer Organization and Architecture13

14. Datatypes VHDL categorizes objects in to four classes  Constant – an object whose value cannot be changed  Signal – an object with a past history  Variable – an object with a single current value  File – an object used to represent a file in the host environment Each object belongs to a type  Scalar (discrete and real)  Composite (arrays and records)  Access  File Introduction to Computer Organization and Architecture14

15. Hierarchy  Non-trivial designs are developed in a hierarchical form Complex blocks are composed of simpler blocks Introduction to Computer Organization and Architecture15 VHDLVerilog Entity and architectureModule Function ProcedureTask Package and package bodyModule

16. Introduction to Computer Organization and Architecture16  A concurrent language allows for: Multiple concurrent “elements” An event in one element to cause activity in another  An event is an output or state change at a given time  Based on interconnection of the element’s ports Logical concurrency — software True physical concurrency — e.g., “<=” in Verilog Hardware Simulation

17. Introduction to Computer Organization and Architecture17 Discrete Time Simulation Models evaluated and state updated only at time intervals — n   Even if there is no change on an input  Even if there is no state to be changed  Need to execute at finest time granularity  Might think of this as cycle accurate — things only happen @(posedge clock) You could do logic circuits this way, but either:  Lots of gate detail lost — as with cycle accurate above (no gates!)  Lots of simulation where nothing happens — every gate is executed whether an input changes or not.

18. Introduction to Computer Organization and Architecture18 Discrete Event (DE) Simulation Discrete Event Simulation…also known as Event- driven Simulation  Only execute models when inputs change  Picks up simulation efficiency due to its selective evaluation Discrete Event Simulation  Events — changes in state at discrete times. These cause other events to occur  Only execute something when an event has occurred at its input  Events are maintained in time order  Time advances in discrete steps when all events for a given time have been processed

19. Introduction to Computer Organization and Architecture19 Discrete Event (DE) Simulation  Quick example Gate A changes its output. Only then will B and C execute  Observations The elements in the diagram don’t need to be logic gates DE simulation works because there is a sparseness to gate execution — maybe only 12% of gates change at any one time.  The overhead of the event list then pays off A B C

20. Introduction to Computer Organization and Architecture20 Test Benches  Testing a design by simulation  Use a test bench model an architecture body that includes an instance of the design under test applies sequences of test values to inputs monitors values on output signals  either using simulator  or with a process that verifies correct operation

21. Introduction to Computer Organization and Architecture21 Simulation Execution of the processes in the elaborated model Discrete event simulation  time advances in discrete steps  when signal values change—events A processes is sensitive to events on input signals  specified in wait statements  resumes and schedules new values on output signals  schedules transactions  event on a signal if new value different from old value

22. Introduction to Computer Organization and Architecture22 Simulation Algorithm  Initialization phase each signal is given its initial value simulation time set to 0 for each process  activate  execute until a wait statement, then suspend  execution usually involves scheduling transactions on signals for later times

23. Introduction to Computer Organization and Architecture23 Simulation Algorithm  Simulation cycle Advance simulation time to time of next transaction For each transaction at this time  update signal value  event if new value is different from old value For each process sensitive to any of these events, or whose “wait for …” time-out has expired  resume  execute until a wait statement, then suspend  Simulation finishes when there are no further scheduled transactions

24. Introduction to Computer Organization and Architecture24 Synthesis  Translates register-transfer-level (RTL) design into gate-level netlist  Restrictions on coding style for RTL model  Tool dependent

25. Introduction to Computer Organization and Architecture25 Basic VerilogHDL Concepts  Interfaces  Behavior  Structure

26. A Gate Level Model  A Verilog description of an SR latch module nandLatch (outputq, qBar, inputset, reset); nand #2 g1 (q, qBar, set), g2 (qBar, q, reset); endmodule A module is defined name of the module The module has ports that are typed primitive gates with names and interconnections type and delay of primitive gates 26Introduction to Computer Organization and Architecture

27. 27 A Behavioral Model - FSM X Q2 Q1 Q2’ D1 Q1 D2 Q2 Z clock reset

28. Introduction to Computer Organization and Architecture28 Verilog Organization for FSM  Two always blocks One for the combinational logic — next state and output logic One for the state register

29. Introduction to Computer Organization and Architecture29 module FSM (x, z, clk, reset); inputclk, reset, x; outputz; reg[1:2]q, d; regz; endmodule Verilog Behavioral Specification always @(x or q) begin d[1] = q[1] & x | q[2] & x; d[2] = q[1] & x | ~q[2] & x; z = q[1] & q[2]; end always @(posedge clk or negedge reset) if (~reset) q <= 0; else q <= d; The sequential part (the D flip flop) The combinational logic part next state output The combinational logic part next state output

30. SystemVerilog Introduction to Computer Organization and Architecture30

31. Verilog-95 Introduction to Computer Organization and Architecture31

32. VHDL Much Richer Than Verilog Introduction to Computer Organization and Architecture32

33. C Can’t Do Hardware Introduction to Computer Organization and Architecture33

34. Verilog-2001 Introduction to Computer Organization and Architecture34

35. Verification and Modeling Introduction to Computer Organization and Architecture35

36. SystemVerilog: Unified Language Introduction to Computer Organization and Architecture36

37. Typical Digital System Structure Execution Unit (Datapath) Control Unit (Control) Data Inputs Data Outputs Control Inputs Control Outputs Control Signals 37Introduction to Computer Organization and Architecture

38. Execution Unit (Datapath)  Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task  Examples of Resources Adders, Multipliers, Registers, Memories, etc. 38Introduction to Computer Organization and Architecture

39. Control Unit (Control)  Controls Data Movements in an Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources  Follows Some ‘Program’ or Schedule  Often Implemented as Finite State Machine or collection of Finite State Machines 39Introduction to Computer Organization and Architecture

40. Finite State Machines (FSMs)  Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs  Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization 40Introduction to Computer Organization and Architecture

41. Moore FSM  Output Is a Function of a Present State Only Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset 41Introduction to Computer Organization and Architecture

42. Mealy FSM  Output Is a Function of a Present State and Inputs Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset 42Introduction to Computer Organization and Architecture

43. Moore Machine state 1 / output 1 state 2 / output 2 transition condition 1 transition condition 2 43Introduction to Computer Organization and Architecture

44. Mealy Machine state 1 state 2 transition condition 1 / output 1 transition condition 2 / output 2 44Introduction to Computer Organization and Architecture

45. Moore vs. Mealy FSM (1)  Moore and Mealy FSMs Can Be Functionally Equivalent Equivalent Mealy FSM can be derived from Moore FSM and vice versa  Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area 45Introduction to Computer Organization and Architecture

46. Moore vs. Mealy FSM (2)  Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM  Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is more likely to have a shorter critical path 46Introduction to Computer Organization and Architecture

47. Moore FSM - Example 1  Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / 1 0 0 0 1 1 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed S2: “10” observed 47Introduction to Computer Organization and Architecture

48. Mealy FSM - Example 1  Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed 48Introduction to Computer Organization and Architecture

49. Moore & Mealy FSMs - Example 1 clock input Moore Mealy 0 1 0 0 0 S0 S1 S2 S0 S0 S0 S1 S0 S0 S0 49Introduction to Computer Organization and Architecture

50. FSMs in VHDL  Finite State Machines Can Be Easily Described With Processes  Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the clock process 50Introduction to Computer Organization and Architecture

51. Moore FSM process (clock, reset) Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset concurrent statements 51Introduction to Computer Organization and Architecture

52. Mealy FSM process (clock, reset) Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset concurrent statements 52Introduction to Computer Organization and Architecture

53. Moore FSM - Example 1  Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / 1 0 0 0 1 1 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed S2: “10” observed 53Introduction to Computer Organization and Architecture

54. Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF; 54Introduction to Computer Organization and Architecture

55. Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’; 55Introduction to Computer Organization and Architecture

56. Mealy FSM - Example 1  Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset 56Introduction to Computer Organization and Architecture

57. Mealy FSM in VHDL (1) TYPE state IS (S0, S1); SIGNAL Mealy_state: state; U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF; 57Introduction to Computer Organization and Architecture

58. Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’; 58Introduction to Computer Organization and Architecture

59. Cz1=  resetn Bz0=  Az0=  w0= w1= w1= w0= w0= w1= Moore FSM - Example 2 State Diagram 59Introduction to Computer Organization and Architecture

60. Present Next state Output state w=0w=1 z AAB0 BAC0 CAC1 Moore FSM - Example 2 State Table 60Introduction to Computer Organization and Architecture

61. Moore FSM process (clock, reset) Present State Register Next State function Output function Input: w Present State: y Next State Output: z clock resetn concurrent statements 61Introduction to Computer Organization and Architecture

62. USE ieee.std_logic_1164.all ; ENTITY simple IS PORT (clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN Moore FSM - Example 2 VHDL (1) 62Introduction to Computer Organization and Architecture

63. IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; Moore FSM - Example 2 VHDL (2) 63Introduction to Computer Organization and Architecture

64. WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; Moore FSM - Example 2 VHDL (3) 64Introduction to Computer Organization and Architecture

65. Moore FSM Present State Register Next State function Output function Input: w Present State: y_present Next State: y_next Output: z clock resetn process (w, y_present) concurrent statements process (clock, resetn) 65Introduction to Computer Organization and Architecture

66. ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; Alternative Example 2 VHDL (1) 66Introduction to Computer Organization and Architecture

67. WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; Alternative Example 2 VHDL (2) 67Introduction to Computer Organization and Architecture

68. PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Alternative Example 2 VHDL (3) 68Introduction to Computer Organization and Architecture

69. A w0=z0=  w1=z1=  B w0=z0=  resetn w1=z0=  Mealy FSM - Example 2 State Diagram 69Introduction to Computer Organization and Architecture

70. Present Next stateOutput z state w=0w=1w=0w=1 AAB00 BAB01 Mealy FSM - Example 2 State Table 70Introduction to Computer Organization and Architecture

71. Mealy FSM process (clock, reset) Next State function Output function Input: w Present State: y Next State Output: z Present State Register clock resetn concurrent statements 71Introduction to Computer Organization and Architecture

72. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN Mealy FSM Example 2 VHDL (1) 72Introduction to Computer Organization and Architecture

73. PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; Mealy FSM Example 2 VHDL (2) 73Introduction to Computer Organization and Architecture

74. WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others; END Behavior ; Mealy FSM Example 2 VHDL (3) 74Introduction to Computer Organization and Architecture

75. State Encoding  State Encoding Can Have a Big Influence on Optimality of the FSM Implementation No methods other than checking all possible encodings are known to produce optimal circuit Feasible for small circuits only  Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool 75Introduction to Computer Organization and Architecture

76. Types of State Encodings (1)  Binary (Sequential) – States Encoded as Consecutive Binary Numbers Small number of used flip-flops Potentially complex transition functions leading to slow implementations  One-Hot – Only One Bit Is Active Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs 76Introduction to Computer Organization and Architecture

77. Types of State Encodings (2) StateBinary CodeOne-Hot Code S000010000000 S100101000000 S201000100000 S301100010000 S410000001000 S510100000100 S611000000010 S711100000001 77Introduction to Computer Organization and Architecture

78. The End Lecture 3