1. WP4 – Optical Processing Sub-System Development Start M06, finish M30 UCC lead Plans for next 6 months: –Complete assembly of integrated hybrid circuits –Design, fab & assemble versions with integrated delay loops using feedback from 1 st versions

2. WISDOM WP4 CIP Activity Fabrication of integrated pattern matching motherboards Fabrication of self-correcting daughterboards Fabrication of band-gap shifted 3mm SOAs Fabrication of substrate free thin film filters

3. Circuit Schematics Using existing pattern matching circuit as template, custom hybrid version will initially be split into two parts and use fibre as the interconnect Stage 1 hybrid

4. Circuit Schematics (2) Half of pattern matching circuit refined with inclusion of on chip preamplifiers, tuneable splitters and taps, and thin film filters 10ps

5. Motherboard Circuit layout Real motherboard

6. New Daughterboards Self correcting daughterboard designs 2mm and 3mm versions

7. 3mm SOAs MQW redesign –Shift band-edge to shorter wavelengths –Larger phase modulation, smaller amplitude modulation in C-band Devices fabricated and tested by UCC

8. Thin Film Filter Stress balanced TFF design –Substrate removed post deposition –70 layer stack –20-30 micron thick –Filter inserted directly into slot cut in waveguides

9. Next 6 months WP4 will extend beyond M30 – probably out to M36 (assuming 6 month extension to project) Assemble current pattern matching circuits & test Design and fab integrated versions using feedback from 1 st tests (new motherboards)