1. CS/EE 3700: Fundamentals of Digital System Design Chris J. Myers Spring 2000 - 2001

2. Course Information Class webpage: –www.async.elen.utah.edu/~myers/ee3700 Get handout #1 for class and contact info. Class webboard – see the webpage

3. TAs and Grader Teaching assistants: –David Sanderson –Jian Zhou –James Bergstrom Grader –Dong-Hoon Yoo Lots of office hours, see handout #1.

4. Discussion Sections You must signup for and attend one discussion section. Supplemental material given here to help with homework and labs. Written assignments will be returned in your discussion section. Sections start Wednesday.

5. Course Description Boolean algebra – theory for digital design. Overview of implementation technology. Combinational logic design. Number representations and arithmetic. Sequential logic design – sync and async. VHDL and CAD tools utilized throughout.

6. Prerequisites Computer programming (CS 2010) PHYCS 2220

7. Textbook Fundamental of Digital Logic with VHDL Design – by Brown and Vranesic, 2000.

8. Homework/Labs/Projects Homework/lab/project writeups should be turned in to appropriate EE locker. Put discussion section number and TA on all assignments. Hardware labs checked in discussion section/office hours. Homework returned in your discussion section. All grading disputes must be made within one week of receiving the grade.

9. Late Homework/Cheating No late homework/labs/projects will be accepted. Cheating will be not be tolerated and it will be strongly dealt with. This includes: –Passing off someone else’s hardware as yours. –Copying someone else’s VHDL code. –Copying someone’s homework/exam answers. –etc.

10. Lab Kits Many labs will use lab kits. These include numerous chips, boards, wires, and design tools. Distributed during first discussion section.

11. Grading Policy Homework and Labs – 30 percent Midterms – 30 percent Project – 20 percent –A simple microprocessor Final – 20 percent –Tuesday, May 1 st, 7:00-9:00am

12. CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 1: Design Concepts Chapter 1

13. Chip Complexity 1963: transistor size = 50  m 1mm 4 km MEB Ft. Douglas

14. Chip Complexity 1975: transistor size = 10  m 5mm 100 km Salt Lake Provo

15. Chip Complexity 1985: transistor size = 2  m 10mm1000 km NV UT

16. Chip Complexity 1995: transistor size = 0.4  m 15mm 7500 km North America

17. SIA Roadmap YEAR 199920012003200620092012 xtor size (  m) 0.140.120.100.070.050.035 xtor/cm 2 (million) 1416244064100 Chip size (mm 2 ) 800850900100011001300

18. Figure 1.1 A silicon wafer

19. Standard Chips Realize common logic functions. Usually less than 100 transistors. Many common ones found in your lab kits. You will use them in a couple of labs. Not used much today as they occupy too much space on printed circuit boards (PCB).

20. Programmable Logic Devices They can realize much more complicated logic circuits than a standard chip. Often reprogrammable. Field-programmable gate arrays (FPGA) will soon use more than 100 million xtors. Widely used today. You will use in one lab and your project.

21. Figure 1.2 A field-programmable gate array chip Memory block Group of 8 logic cells Interconnection wires

22. Custom-designed Chips PLDs are not very efficient so they may not meet performance or cost objectives. May need to design a custom or semi- custom chip (also known as an ASIC). Advantage: optimized for given task. Disadvantage: more complex design and manufacturing process. Custom VLSI design taught in CS/EE 5710.

24. Figure 1.3 The development process Required product Design specifications Initial design Simulation Design correct? Redesign Prototype implementation Testing Meets specifications? Finished product Minor errors? Make corrections No Yes No Yes No

25. Design concept Successful design Initial design Simulation Design correct? Redesign No Yes Figure 1.4 The basic design loop

26. Figure 1.5 A printed circuit board

27. Figure 1.6 Design flow for logic circuits Design interconnection between blocks Functional simulation of complete system Correct? Physical mapping Timing simulation Correct? Implementation No Yes No Yes Design one block Partition Design concept A B C D

28. Figure 1.7 Completion of PCB development Implementation Finished PCB Build prototype Testing Correct? Modify prototype No Yes Minor errors? Yes Go to A, B, C, or D in Figure 1.6 No

29. Theory and Practice Numerous CAD tools available for design. Why study the theory and not just the tools? –Designer must provide good specification. –This theory is utilized in these tools, and it helps you understand what the tools do. –Designer must understand the effects of optional processing steps. –It is intellectually challenging.