1. TAMES2-Workshop R&D for Embedded Analogue Testing Diego Vázquez García de la Vega Instituto de Microelectrónica de Sevilla (IMSE-CNM) dgarcia@imse.cnm.es

2. Diego Vázquez IMSE-CNM TAMES2-Workshop Outline A panoramic view Analogue and MS Test. Current Status External Testing. Fundamental Problems Solutions Conclusions

3. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View Projections: SIA ROADMAP

4. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View FROM ASICs to SOCs RF circuitry Power Management Passive Components Next SOCs And… increased performance in terms of speed, bandwidth, accuracy, power, voltage supply, etc… MS SoC (00’s) DSP Memory Wired Communication Wireless Communication Audio & Video Glue Logic ProcessorMemory Digital SoC (90’s) Application Specific Logic ASIC (80’s)

5. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Board (SOB) Dedicated technologies Pre-tested ICs (dedicated tester) Board level test uP Memory Mixed Signal digital RF Functional Tester Logic Tester Memory Tester Mixed-Signal Tester RF Tester

6. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) Mixed technologies on the same chip Pre-designed blocks (not tested) Core and IC level Test required uP Memory Mixed Signal digital RF SOC evolution: Standard Blocks Reusable (IP) Blocks uP Memory Mixed Signal digital RF System-On-Board (SOB)

7. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) Mixed technologies on the same chip Pre-designed blocks (not tested) Core and IC level Test required uP Memory Mixed Signal digital RF uP Memory Mixed Signal digital RF System-On-Board (SOB) Dedicated technologies Pre-tested blocks Board level test

8. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) uP Memory Mixed Signal digital RF Different cores with different modeling, different test requirements, different tester languages, etc. Std BlocksIP Blocks Functional Tester Logic Tester Memory Tester Mixed-Signal Tester RF Tester

9. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View uP Memory Mixed Signal digital RF IP Core-Based System Design and Test Development Manufacturing Test Core provider System integrator IP-Core-Based approach  Core Provider may not know: Which test method, tolerance margins, etc. to use.  System integrator may have: Very limited knowledge of the adopted core.  Test of embedded IP cores: Joint responsibility of both core provider and system integrator.

10. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) uP Memory Mixed Signal digital RF More to Test !!!!! Source: SIA Roadmap

11. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) uP Memory Mixed Signal digital RF Less Test Access !!!!! Source: SIA Roadmap

12. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) uP Memory Mixed Signal digital RF Bandwidth Gap !!!!! Source: SIA Roadmap 30% per year 12% per year aprox.

13. Diego Vázquez IMSE-CNM TAMES2-Workshop A Panoramic View System-On-Chip (SOC) uP Memory Mixed Signal digital RF Increased Bandwidth !!! Source: SIA Roadmap

14. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Current Status FUNCTIONAL TEST Stimuli Generator CUT Response Interpreter Specification-Based Test The Circuit Complies Specs The CUT is considered as a black box All interesting I/O relationship must be checked out Tests may overlap and be redundant It takes long time It requires different instrumentation Tests do not guarantee defect-free ICs I/O Behavior

15. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Current Status Analog Circuit classes: –Filters –ADCs –DACs –PLLs –RF Transceivers –Signal Conditioners –etc Testing methods is circuit dependent: –Filters Frequency domain, Passband, Rejection band, Distortion, Dynamic Range, etc. –Data Converters Time domain, Linearity (INL, DNL), SNR, ENB, etc. –PLLs Frequency Domain, Stability, Capture Range, Jitter, etc. –Basic Blocks (OTAs, Opamps, etc) DC, AC, Transient, etc. Combined into an IC requires different test techniques:  Test stimuli  Response analysis

16. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Current Status Specification-based (functional) tests: Tractable and does not need an analog fault model. –Long test development time –Expensive ATE –Long test time. Test stimuli: –Multiple types –Dependence wrt to the involved circuit Test evaluation: –Multiple types (DC, AC, Transient, etc.) –Requires accurate and complex post-processing Separate test for functionality and timing impossible.

17. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Current Status uP Memory Mixed Signal digital RF SUPER TESTER Large Pin-Count Large Data Volume High Frequency Features High Accuracy Features etc  Stimuli generation  Precision timing  Diagnostic  Test control  Power management  Large deep memory  Slow throughput  etc.

18. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Alternative Approach Stimuli Generator CUT Response Interpreter STRUCTURAL TEST Defect-Oriented Test There are no defects The CUT structure must be known Minimal test showing up defects It takes shorter times It requires simple instrumentation Tests do not guarantee Specs Defect Effects

19. Diego Vázquez IMSE-CNM TAMES2-Workshop Analogue and MS Test Alternative Approaches FUNCTIONAL TEST Stimuli Generator CUT Response Interpreter Specification-Based Test The Circuit Complies Specs The CUT is considered as a black box All interesting I/O relationship must be checked out Tests may overlap and be redundant It takes long time It requires different instrumentation Tests do not guarantee defect-free ICs I/O Behavior STRUCTURAL TEST Defect-Oriented Test There are no defects The CUT structure must be known Minimal test showing up defects It takes shorter times It requires simple instrumentation Tests do not guarantee Specs Defect Effects Both approaches are complementary

20. Diego Vázquez IMSE-CNM TAMES2-Workshop Fundamental problems with External Testing  More to Test but Less Test Access uP Memory Mixed Signal digital RF More Devices and less Pin/Device

21. Diego Vázquez IMSE-CNM TAMES2-Workshop Fundamental problems with External Testing  More to Test but Less Test Access  Yield Losses Source: SIA Roadmap Device speed +30% per year Tester accuracy 12% per year Projected Yield losses If current trends continue, in less than ten years, tester timing errors will approach the cycle time of the fastest devices.

22. Diego Vázquez IMSE-CNM TAMES2-Workshop Fundamental problems with External Testing  More to Test but Less Test Access  Yield Losses  ATE Cost Accuracy, Bandwidth, noise, pin-count, socket performance, memory, etc. accordingly to CUT. If current trends continue, it may cost more to test a transistor than to manufacture the transistor (by 2014).

23. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions Lines of interest Standardized Test Access Mechanism »1149.4 »P1500* Structured Test planning »Enable hierarchical testing »Enable the re-use of on-chip resources (DSP, uP, etc.) »Facilitate parallel testing »etc. Re-usable and structured DfT & BIST techniques » Provide accessing to embedded cores, » Reduce I/O data rate requirements, » Enable low pin count testing, and » Reduce the dependence on expensive instruments.

24. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions Standard Test Access efforts  1149.4 (started at the end of 1991) –Standard Mixed-Signal test bus to be used at device, sub-assembly and system levels. »Aims to increase the observability and controllability of Mixed-Signal designs and support MS-BIST structures.  P1500 (started in 1995) –Standard test method for embedded cores. »Focused on Standardized Core Test Language (CTL) and configurable & scalable test wrapper for easy test access to the core. »Need extension to mixed-signal.

25. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions: Standardized Test Access Mechanism: 1149.4 Standard Mixed-Signal test bus to be used at device, sub-assembly and system levels. –Aims to increase the observability and controllability of Mixed-Signal designs and support MS-BIST structures.

26. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions: sw-opamp Solution for internal accessing to opamp-based circuits. –Control and observability Control: Test Stimuli application Control&Observation: Test Stimuli application & Response propagation

27. Diego Vázquez IMSE-CNM TAMES2-Workshop I/O Test Interface 2nd SOC generation Structured Test planning Further research required! Today SOCs are the tomorrow cores!! 1st SOC generation I/O Test Interface 3rd SOC generation

28. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions DfT & BIST Re-usable and structured DfT & BIST techniques. A DfT Technique is not a Test Technique. An optimum strategy requires a synthesis of different DFT & BIST techniques. Physical Electrical Block System Layout Rules & guidelines Support for specif. meas. isolation & accessing Pre/Post processing tech. Partial / full BIST On-line Test General Circuit Specific Hierarchy Techniques

29. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions DfT & BIST Re-usable and structured DfT & BIST techniques. An optimum strategy requires a synthesis of different DFT & BIST techniques. Physical Electrical Block System Layout Rules & guidelines Support for specif. meas. isolation & accessing On-Chip techniques Partial / full Self-Test Concurrent Test Hierarchy Techniques Layout Optimization Design for Iddq Sw-opamp Standard Test Bus (1149.4) ADCBIST, PLLBIST MADBIST, HBIST Circuit Reconfiguration Self-Checking archit. On-Line Archit. Examples

30. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions DfT & BIST Re-usable and structured DfT & BIST techniques. Physical Electrical Block System Layout Rules & guidelines Support for specif. meas. isolation & accessing On-Chip techniques Partial / full Self-Test Concurrent Test Hierarchy Techniques Layout Optimization Design for Iddq Sw-opamp Standard Test Bus (1149.4) ADCBIST, PLLBIST MADBIST, HBIST Circuit Reconfiguration Self-Checking archit. On-Line Archit. ExamplesStructural Functional Accessing

31. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions BIST MAIN ADVANTAGES –Test the untestable: Embedded cores Measure functions faster than ATE –IP protection –Re-usability: Along IC life cycles: wafer, board, field –Reduce ATE requirements –Reduce test development and application time REQUIREMENTS –Put ATE functions into the chip: Test stimuli generation Output response analysis Test control –Support for Board and System levels. –Extra Area TECHNIQUES: –Functional: Meas Specs. params –Structural: Detect faults and predict yield. EXAMPLES: HBIST (functional), OBIST (functional & structural), MADBIST (functional), adcBIST, PLLBIST, etc.

32. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions BIST MAIN ADVANTAGES –Test the untestable: Embedded cores Measure functions faster than ATE –IP protection –Re-usability: Along IC life cycles: wafer, board, field –Reduce ATE requirements –Reduce test develop.&Applic. time REQUIREMENTS –Put ATE functions into the chip: Test stimuli generation Output response analysis Test control –Support for Board and System levels. –Extra Area –Design Efforts

33. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions BIST TECHNIQUES: –Functional: Meas Specs. Params –Structural: Signature analysis to detect faults and predict yield problems. EXAMPLES HBIST [Ohletz91] MADBIST[Toner&Roberts,93] adcBIST [LogicVision] PLLBIST [LogicVision] adcBISTmaxx [Opmaxx] –OBIST (filters, ADCs, DACs,  -mod, etc.) –Reconfiguration (filters,  -mod, Pipeline ADCs, etc.) –Etc.

34. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions Test Stimuli Generators Available techniques –Sinusoidal oscillators –Relaxation oscillators –Digital synthesizers –  –based Bit-streams generators –White noise generators –PWM generators –Etc. Constrains –Precission & Resolution –Frequency range –Multi-tone capability –Linearity (ramps) –Calibration –Programmability –Area –Etc.

35. Diego Vázquez IMSE-CNM TAMES2-Workshop Solutions Output Response Analyzers Available techniques –Histograms –FFT –Bandpass digital filters –  Signature analyzer –Sinewave correlation –Etc. AD DSP (FFT) AD Passband DIGITAL FILTER Reject Band Signal Power Noise Power

36. Diego Vázquez IMSE-CNM TAMES2-Workshop Conclusions DfT&BIST vs External ATE Reasons for DfT&BIST –Portable: reusable along IC life cycle –The only solution for embedded blocks –Reduce cost of external ATE –At-Speed Test –Solves SOCs problems (accessing, IP protection) –Simplifies Test Program Development –External accessing to embedded blocks may impact performance Reasons for External ATE –External ATE can do more testing –BIST increase IC complexity –BIST may impact performance –BIST increase design efforts & time –BIST may increase yield loss.

37. Diego Vázquez IMSE-CNM TAMES2-Workshop Conclusions Further Research required: DfT & BIST techniques for analogue embedded cores  Many companies and researchers are providing since some years good solutions for a diversity of cores (PLLs, ADCs and DACs, filters, memories, etc.).  However, the industry has only adopted standards (1149.4) & functional solutions (adc-BIST, adcBISTmaxx, etc.)  Structural techniques not widely accepted, but they are a clear potential solution that need to be further explored.

38. Diego Vázquez IMSE-CNM TAMES2-Workshop On-Chip Test Manager  Stimuli generation  Result compression  Precision timing  Diagnostic  Power manager  Test Control  Support for board & system level Memory (BISTed) Logic (BISTed) Mixed-Signal (BISTed) I/O & Interconnects (BISTed) IC Conclusions DfT & BISTed ICs NEED!!: Dedicate part of the IC area to include DfT and BIST facilities External ATE Digital Tester Low cost-per-pin Limited speed Limited accuracy External ATE Digital Tester Low cost-per-pin Limited speed Limited accuracy High Bandwidth internal interfaces Low Bandwidth external interfaces Ideal concept: DfT & BISTed IC