1. Designing with External Flash Memory on Renesas Platforms
Douglas Crane, Segment Manager
Micron Technology
CL23A

2. Douglas Crane
Doug is a 27 year veteran in the electronics field. He currently works for Micron Technology as a Sr. Segment Manager driving application strategies, enabling the memory sub-system ecosystem and identifying roadmap requirements for embedded solutions group. Doug has been in the memory business for 16 years, 6 of which is with Micron and 10 with Toshiba in technical marketing roles for memory products. Prior to his memory experience, he spent 11 years involved in systems engineering at McDonnell Douglas and Rockwell. Doug has a BS in Applied Physics from University of California Irvine, MSEE from Cal State Fullerton, and an MBA from the University of Southern California. Doug has been involved in memory standards committee of JEDEC as well as been in the JEDEC board of directors

3. Renesas Technology & Solution Portfolio
The wealth of technology you see here is a direct result of the fact that Renesas Electronics Corporation was formed on April 1, 2010 as a joint venture between Renesas Technology and NEC Electronics — Renesas Technology having been launched seven years ago by Hitachi, Ltd. and Mitsubishi Electric Corporation. There are four major areas where Renesas offers distinct technology advantage.
--The Microcontrollers and Microprocessors are the back bone of the new company. Renesas is the undisputed leader in this area with 31% of W/W market share.
--We do have a rich portfolio of Analog and power devices. Renesas has the #1 market share in low voltage MOSFET solutions.
--We have a rich portfolio of ASIC solution with an advanced 90nm, 65nm, 40nm and 28nm processes. The key solutions are for the Smart Grid, Integrated Power Management and Networking
--ASSP: Industry leader for USB 2.0 and USB 3.0. Solutions for the cell phone market
-- Memory: #1 in the Networking Memory market

4. Agenda Market Trends System Considerations Flash Cell Architectures
RX62N PCM Demo
Flash Memory Choices
Summary

5. 2012 Semiconductor Market Forecast
Source: Gartner 3Q11

6. Memory Subsystem Designs/Architecture
Execute in Place (XIP) Architecture
“Store and Download” (SnD) Architecture
Boot
Data
&
Files
NAND
xRAM
Working
Static
Shadow
Code copied and fixed in place at boot
NOR
MCU
Memory/Bus
Controller I$ D$
MCU
Memory/Bus
Controller I$ D$
Code
Data
Flash
xRAM
Working
Static
Flash
Flash
xRAM
xRAM
Simple architecture
Possible to reduce xRAM density
Lower stand-by power
Complex but higher performance
More xRAM required
Higher stand-by power

7. Platform Memory Mapping
Internal Flash
External Flash Memory
SNOR
PNOR
Managed NAND
x32
RH850
256K-8MB
V850
16KB-2MB RX
32K-2MB
128Mb
SuperH
SH2/2A
16K-2MB
SH4/4A X
H8SX
128K-1MB
X8/ x16
RL78
2KB-512KB
8Mb
SoC
R Car H1
eMMC
R Car M1x

8. System Cost Reductions and Simplification
Software Architecture
System Architecture
N+1 N
NVM
RAM
Boot Code
+ OS
Shadowed
Code High Read
N+2
Critical
Data
N+3
High
Write
Memory Banks
Complimentary I/O
CPU
Main Memory E2
NOR/NAND
BatRAM/nvRAM
Understand your usage model
xRAM usage models
How many CE#/banks do you use
Why might you split memory into separate chips
Other system SW requirements (file system, data logging, etc)
System BOM
Can you eliminate or partially eliminate any unnecessary memory?
Performance vs. Cost ratio

9. Larger Data Fetches

10. Performance Comparison – Small Data

11. Cell Architectures Floating Gate Technologies PCM Technology
Electron Storage
PCM
Technology

12. PCM Benefits Bit alterability Scaling Endurance Bit Errors 1 11
No erase required 1
90 & 45nm today
5nm future
Endurance
Bit Errors

13. Hardware Setup Embedded components: Enter
Renesas RX62N development board
Embedded components:
RX62N microcontroller
Micron SPI (P5Q)
Additional components
Micron SPI (M25P)
128Mb NOR SPI
(M25P)
Revise picture of the board
USB use for power only
Computes
Electrical outlet
Enter
128Mb PCM SPI
(P5Q)
arrow up button
arrow down button
enter button

14. Micron/Renesas Software
Comparing NOR vs PCM
NOR SPI
Industry erase & program
PCM SPI
PCM specific commands
Data outputted
Erase time
Program time
Assumptions:
Image size (2-Mbytes)
Clock frequency (30-MHz)
Single I/O
Choosing NOR (M25P)
Choosing PCM (P5Q)
Program Method
Erase time = Seconds
Program time = Seconds
Output data

15. Experiment #1 … “NOR vs. PCM”
Product background:
Product Frequency Erase Size Program Size Program Command Cycles
M25P MHz Mb Bytes h ,000
P5Q MHz Mb Bytes h ,000,000
Data collected:
SF PMOD (M25P16) “Erase Before Program”
SF2 PMOD (P5Q128) “Erase Before Program”
Variables
Image size, SPI mode & frequency
Lessons learned:
3x improvement with minimal software changes

16. What is “Program on All 1’s”
Floating Gate “Program”
D1h
PCM “Program on ALL 1’s”
Erase Block
Erase Block
Program Data
Program Data

17. Experiment #2 “Program on All 1’s”
Product background:
Product Frequency Erase Size Program Size Program Command Cycles
M25P MHz Mb Bytes h ,000
P5Q MHz Mb Bytes D1h ,000,000
Data collected:
SF PMOD (M25P16) “Erase Before Program”
SF2 PMOD (P5Q128) “Program on All 1’s”
Variables
Image size, SPI mode & frequency
Lessons learned:
D1h is a smaller software change than 22h to get 4x improvement
In-system program command can be used to improve performance

18. What is “Bit Alterable Write”
Floating Gate Program
22h
PCM Bit Alterable Write
YES! X
NO!
Erase Block
Bit Alterable Write
Program Data
Faster performance
Easier data manipulation

19. Experiment #3 “Bit Alterable Write”
Product background:
Product Frequency Erase Size Program Size Program Command Cycles
M25P MHz Mb Bytes h ,000
P5Q MHz Kb Bytes h ,000,000
Data collected:
SF PMOD (M25P16) “Erase Before Program”
SF2 PMOD (P5Q128) “Bit Alterable”
Variables
Image size, SPI mode & frequency
Lessons learned:
PCM Bit alterability improves performance by 10x

20. Experiment #4 “Test Your Endurance”
Product background: *Definition of Cycle: Floating Gate vs. PCM*
Product Frequency Erase Size Program Size Program Command Cycles
M25P MHz Mb Bytes h ,000
P5Q MHz Kb Bytes h or 22h 1,000,000
Data collected:
SF2 PMOD (P5Q128) “Erase Before Program” or “Bit Alterable”
SF PMOD (M25P16) “Erase Before Program”
Variables
Image size, SPI mode & frequency
Lessons learned:
PCM offers 10x endurance vs. NOR

21. Data Summary & Brainstorming
3x Faster
4x Faster
6x Faster
What application would PCM go into today

22. Your Own Development Board
Link here to get your board or talk to your Renesas representative

23. Solutions for Different Requirements
NOR vs. NAND
Lowest Floor Cost ($)
Lowest
$/GB
Serial NOR
Parallel NOR
SLC NAND
Managed NAND
MLC
NAND
Longer lifecycles
Ease of use
Diverse products
Lower Floor cost
Code, Code+Data
Shorter lifecycles
Focus on cost/GB
Expanding markets
Mostly Data Focused
Customer requirements dictate the solution

24. NOR Product Attributes
Simple command sets
Cost effective at low densities
Stable architectures
Value added features (XiP, security, quality, small data, etc)
Serial
Low pin counts
Easy PCB routing
Smallest footprint
Synchronous operations
Cheapest low density
Parallel
Basic add/data interface
Asynchronous random access
Synchronous burst operations
Higher throughput
Best XiP architecture

25. NAND Product Attributes
Low pin counts
Cheapest cost/bit at high densities
Frequent conversions/migrations required
Fast programming
Discrete
Some controllers support boot
Some standards (ONFI)
Common packages
Needs SW for error management
Demand paging – saves bits
Managed
Error management onboard
Some controllers support boot
Higher density reach
Easier conversions/migrations
Standards (MMC, USB, uSD…)

26. Flash Architectures – Component Level
All architectures have their advantages
Trend in the industry moving toward the lower pin count architectures

27. NAND Technology Challenges
How to manage the ECC requirements?
NAND controllers with high ECC capability
ECC NAND managed solutions
on-die ECC, ClearNAND
Fully managed solutions
eMMC, eUSB, others
How to manage lower endurance?
Understand the application and usage model
How does the file system work?
How often are you programming?
How big is the data file/s?
What is the PLC of your system?
Determines PE Cycles and
density required
Intersecting your project and the memory technology is key to success!

28. NAND System Solutions for Industry
Raw NAND
Host Controller I
NAND Interface
LLD
ECC
FTL
NAND BUS
Raw NAND for application “expert” with NAND data
management and ready to support ECC needs.
ECC NAND
Host Controller II
NAND Interface
LLD
FTL
NAND BUS
ECC
ECC NAND for application that do not want to change the
ECC with the NAND litho shrink.
SPI
ECC
Host Controller III
SPI Interface
LLD
SPI BUS
FTL
Serial NAND for application requiring high density with
serial protocol.
eMMC NAND
ECC
FTL
Host Controller IV
eMMC Interface
LLD
MMC BUS
eMMC interface for application that want to offload by any
NAND data management with a standard interface.
eUSB NAND
ECC
FTL
Host Controller V
eUSB Interface
LLD
USB BUS
eUSB interface for application that want to offload by any
NAND data management with a standard interface.

29. Memory Technology Comparison
Attributes
PCM
DRAM
NAND
NOR
EEpROM
Bit Alterable
Non-volatile
Cost
Read Speed
Write Speed
All memory technologies have their advantages
Look for ways to differentiate and stay cost effective

30. Understand memory usage Understand true cost
Summary
Customer Next Steps
Understand memory usage
Understand true cost
Work with a trustworthy supplier
Supplier Identification
Provides technology leadership & product longevity
Architecture transparency
Systems expertise & silicon/solution standards

31. Questions?

32. Please Provide Your Feedback…
Please utilize the ‘Guidebook’ application to leave feedback or
Ask me for the paper feedback form for you to use…