1. Lecture 20: Exam 2 Review November 21, 2013 ECE 636 Reconfigurable Computing Lecture 20 Exam 2 Review

2. Lecture 20: Exam 2 Review November 21, 2013 PRISC °Architecture: couple into register file as “superscalar” functional unit flow-through array (no state)

3. Lecture 20: Exam 2 Review November 21, 2013 PRISC Results °All compiled °working from MIPS binary °<200 4LUTs ? 64x3 °200MHz MIPS base Razdan/Micro27

4. Lecture 20: Exam 2 Review November 21, 2013 Chimaera Start from Prisc idea. -Integrate as a functional unit -No state -RFU Ops (like expfu) -Stall processor on instruction miss Add -Multiple instructions at a time -More than 2 inputs possible Hauck: University of Washington

5. Lecture 20: Exam 2 Review November 21, 2013 Chimaera Architecture Live copy of register file values feed into array Each row of array may compute from register of intermediates Tag on array to indicate RFUOP

6. Lecture 20: Exam 2 Review November 21, 2013 Chimaera Architecture Array can operate on values as soon as placed in register file. Logic is combinational When RFUOP matches -Stall until result ready -Drive result from matching row

7. Lecture 20: Exam 2 Review November 21, 2013 Chimaera Results Three Spec92 benchmarks -Compress 1.11 speedup -Eqntott 1.8 -Life 2.06 Small arrays with limited state Small speedup Perhaps focus on global router rather than local optimization.

8. Lecture 20: Exam 2 Review November 21, 2013 Garp Integrate as coprocessor -Similar bandwidth to processor as functional unit -Own access to memory Support multi-cycle operation -Allow state -Cycle counter to track operation Configuration cache, path to memory

9. Lecture 20: Exam 2 Review November 21, 2013 Garp – UC Berkeley ISA – coprocessor operations -Issue gaconfig to make particular configuration present. -Explicitly move data to/from array -Processor suspension during coproc operation -Use cycle counter to track progress Array may directly access memory -Processor and array share memory -Exploits streaming data operations -Cache/MMU maintains data consistency

10. Lecture 20: Exam 2 Review November 21, 2013 Garp Instructions Interlock indicates if processor waits for array to count to zero. Last three instructions useful for context swap Processor decode hardware augmented to recognize new instructions.

11. Lecture 20: Exam 2 Review November 21, 2013 Garp Array Row-oriented logic Dedicated path for processor/memory Processor does not have to be involved in array-memory path

12. Lecture 20: Exam 2 Review November 21, 2013 Garp Results General results -10-20X improvement on stream, feed- forward operation -2-3x when data dependencies limit pipelining - [Hauser-FCCM97]

13. Lecture 20: Exam 2 Review November 21, 2013 PRISC/Chimaera vs. Garp Prisc/Chimaera -Basic op is single cycle: expfu -No state -Could have multiple PFUs -Fine grained parallelism -Not effective for deep pipelines Garp -Basic op is multi-cycle – gaconfig -Effective for deep pipelining -Single array -Requires state swapping consideration

14. Lecture 20: Exam 2 Review November 21, 2013 Common Theme To overcome instruction expression limits: -Define new array instructions. Make decode hardware slower / more complicated. -Many bits of configuration… swap time. An issue -> recall tips for dynamic reconfiguration. Give array configuration short “name” which processor can call out. Store multiple configurations in array. Access as needed (DPGA)

15. Lecture 20: Exam 2 Review November 21, 2013 Observation All coprocessors have been single-threaded -Performance improvement limited by application parallelism Potential for task/thread parallelism -DPGA -Fast context switch Concurrent threads seen in discussion of IO/stream processor Added complexity needs to be addressed in software.

16. Lecture 20: Exam 2 Review November 21, 2013 FPGA Power Reduction Goals Dynamic power goals -Reduce Vdd along non-critical paths -Low swing signalling -Use CAD approaches to limit long high-toggle paths -P dynamic = 0.5 * C * Vdd 2 * f Static power goals -Cut-off Vdd for unused transistors -Use high Vt transistors for SRAM cells -Various other voltage biasing techniques

17. Lecture 20: Exam 2 Review November 21, 2013 Traditional Routing Switch level-restoring buffer Courtesy: Anderson

18. Lecture 20: Exam 2 Review November 21, 2013 Proposed Switch Designs: Anderson °Based on 3 observations: Routing switch inputs tolerant to weak-1 signals (level-restoring buffers). Considerable slack in FPGA designs  many switches can be slowed down. Most routing switches feed other routing switches. -Can produce weak-1 logic signals.

19. Lecture 20: Exam 2 Review November 21, 2013 “Basic” Switch Design high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF MODE OPERATION: V VD

20. Lecture 20: Exam 2 Review November 21, 2013 High-Speed Mode high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF MODE OPERATION: output swing: rail-to-rail. V VD = V DD

21. Lecture 20: Exam 2 Review November 21, 2013 Low-Power Mode high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF MODE OPERATION: output swing: GND-to- (V DD -V TH ). V VD = V DD - V TH V VD output swing: GND-to- (V DD -V TH ).

22. Lecture 20: Exam 2 Review November 21, 2013 Sleep Mode high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF MODE OPERATION: V VD

23. Lecture 20: Exam 2 Review November 21, 2013 Leakage Power Results: Anderson 36 60.8 39.7 38.7 0.3 0 10 20 30 40 50 60 70 LP modeSleep modeLP mode (+unused fanout) LP mode (+used fanout) Traditional switch % leakage power reduction vs. high-speed mode Basic

24. Lecture 20: Exam 2 Review November 21, 2013 FPGA Embedded Memory Blocks °Embedded memory blocks (EMBs) are important parts of FPGAs °Consume roughly 14% of Altera Stratix II dynamic power * Increasing in recent designs * Stratix II Low Power Applications Note, 2005

25. Lecture 20: Exam 2 Review November 21, 2013 Embedded Memory Block Port Internal View Write Data MClk Write Enable Column Mux Write Buffers Sense Amps Row Decode Read Data Read Enable Latch Address MClk Clk Enable Clk RAM cell BIT Bit Line Pre-charge MClk Reducing clocking saves dynamic power

26. Lecture 20: Exam 2 Review November 21, 2013 Power Optimization #1 °Convert EMB read enable/write enable signals to associated read/write clock enable signals °Limitations Each port has read or write enable control signal Embedded memory block has read enable input Clock Wren Data Write Address Read Address Q Write enable Read enable Q Rden Vcc Wr clk enable Rd clk enable Write Address Read Address Clock Wren Data Write Address Read Address Q Write enable Read enable Q Rden Vcc Wr clk enable Rd clk enable Write Address Read Address BeforeAfter

27. Lecture 20: Exam 2 Review November 21, 2013 Implementation °Conversion mode Ties off R/W enable to RAM clock enables Doesn’t make transform if CE already present on port °Combining mode AND user RAM clock enables with derived R/W clock Could impact performance Combined Write Clk Enable Write Enable User-defined Write Clk Enable

28. Lecture 20: Exam 2 Review November 21, 2013 FPGA RAM Processing °FIFOs and Shift registers converted into logical RAMs °Logical RAMs mapped to RAM blocks FIFO, Shift Register, RAM specification Create Logical Memory Logical RAMs/ logic Logical-to- physical RAM processing RAM blocks/ logic Memory/ logic placement Placed Memory

29. Lecture 20: Exam 2 Review November 21, 2013 Mapping RAM to EMBs °Implementation choice can impact design area, performance, and power. °Some mappings may require multiple EMBs 4k deep x 4 wide 16K bits 4K bits M4K User-defined (logical) memory Physical (EMB) memory 512K MRAM

30. Lecture 20: Exam 2 Review November 21, 2013 Memory Organization °Each EMB can be configured to have different depth and width (e.g. Stratix II M4K) °All hold 4K bits °Slightly lower power consumption for wider EMB configurations (not including routing) 4K words deep 1 bit wide 32 bits wide 128 words deep 8 bits wide 512 words deep

31. Lecture 20: Exam 2 Review November 21, 2013 Area and Delay Optimal Mapping °Configure each EMB to be as deep as possible °Number of address bits on each EMB same as on logical memory °Area and performance efficient: no external logic needed °Power inefficient: All EMBs must be active during each logical RAM access 4k words deep and 1 bit wide (4 times) Addr[0:11] Data[0:3] 4k words deep and 4 bits wide Logical memory 4 EMBs active during access EMB Vertical Slicing

32. Lecture 20: Exam 2 Review November 21, 2013 Alternative Mapping °Configure EMB to have width of logical RAM (e.g. 1Kx4) Allows shutdown of some RAMs each cycle But adds some logic °Saves RAM power, adds combinational logic and register power More Power Efficient: 1K deep x 4 wide (4 times) 1 EMB active during access Addr Decoder 4 Addr[0:9] Addr[10:11] Data[0:3] 4k words deep and 4 bits wide Logical memory Addr[10:11] Horizontal Slicing

33. Lecture 20: Exam 2 Review November 21, 2013 RAM Slicing - Example °Power reduction available with different slicing 4kx32 Dynamic Power 0 20 40 60 80 100 120 140 Maximum Depth Dynamic Power (mW) Best range Multiplexer Power Increasing 1282565121k2k4k EMB Power Increasing

34. Lecture 20: Exam 2 Review November 21, 2013 Power Optimization #2: Power-aware RAM Partitioning °Algorithm considers possible logical to physical RAM mappings Completed placement Insert Decode and Mux Logic FIFO, Shift Register Create Logical Memory Power-aware Physical RAM processing Memory/ Logic Placement Power Library

35. Lecture 20: Exam 2 Review November 21, 2013 Experimental Approach °40 designs evaluated °Quartus 5.1 °Mapped to smallest possible device and target max frequency °Simulation with test vectors °Power analysis with PowerPlay

36. Lecture 20: Exam 2 Review November 21, 2013 Experimental Approach °40 designs evaluated °Quartus 5.1 °Mapped to smallest possible device and target max frequency °Simulation with test vectors °Power analysis with PowerPlay

37. Lecture 20: Exam 2 Review November 21, 2013 Memory Power °21.0% average reduction for all techniques (9.7% with convert/combine)

38. Lecture 20: Exam 2 Review November 21, 2013 Overall Core Dynamic Power °6.8% average power reduction for all techniques (2.6% with convert/combine) -5 0 5 10 15 20 25 30 35 13579111315171921232527293133353739 Designs % Dyn. Power Reduction Enable convert/ combine Enable convert/ combine + mem partition

39. Lecture 20: Exam 2 Review November 21, 2013 Design Performance °1.0% average performance loss for all techniques (0.1% for enable convert/combine) Average Design Clock Frequency -30 -25 -20 -15 -10 -5 0 5 10 Designs % Frequency Improvement Enable Convert/ Combine Enable Convert/ Combine + Mem Partition

40. Lecture 20: Exam 2 Review November 21, 2013 Results Summary °Almost 7% core dynamic power reduction across all designs Some designs benefit more than others °Minimal clock frequency hit for most designs Enable convert Enable convert/ combine Enable convert/ combine + Mem partition Core dynamic power -1.8%-2.6%-6.8% Memory dynamic power -6.3%-9.7%-21.0% Max clk freq -0.1%-0.2%-1.0% LUT count 0.0%0.1%0.7%

41. Lecture 20: Exam 2 Review November 21, 2013 Other material °Lecture 17: Reconfigurable Memory Security °Lecture 18: Hardware Monitors to Protect Network Processors °Lecture 19 is not covered on the exam