1. Delay Locked Loop with Linear Delay Element
TELSIKS 2005, Niš
Goran Jovanović, Mile Stojčev and Dragiša Krstić
Faculty of Electronic Engineering, Niš, Serbia and Montenegro

2. Definition of DLL Applications of DLL
DLL circuit is designed for fine, precise, and accurate pulse delay control in a high-speed digital and mixed integrated circuits.
Applications of DLL
achieve correct synchronization between different digital blocks (CPU and SDRAM interface, ...),
eliminate clock skew and jitter within VLSI ICs,
low-jitter clock synthesis,
implementation of Time-to-Digital-Converter with Vernier delay pattern,
PN code tracking in spread spectrum systems…

3. Types of the DLL architecture
The DLL structure is based on a delay element.
According to the principle of delay generation DLL architectures classified as:
analog,
digital, and
hybrid (dual loop)
VCDL – voltage controlled delay line, PD – phase detector,
CP – charge pump, PS – phase selector, FSM – finite state machine

4. Classification of delay line elements
Variable delay line elements are classified as:
Digital- Controlled Delay Elements (DCDEs)
realized as series of delay elements of variable length (the number of elements in a chain determines the amount of the delay).
Voltage-Controlled Delay Elements (VCDEs)
are inverter-based circuits, efficient in applications where small, accurate, and precise amount of delay is necessary to achieve.

5. Common to VCDLs Advantages: Simple structures Fine delay resolution
Disadvantages:
Voltage controlled DLs have non-linear transfer function, delay variation in term of control voltage
Problem of VCDL realization was considered by:
Y. Moon, et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE JSSC, vol.35, No. 3, pp , March 2000.
M. Maymandi-Nejad, M. Sachdev, “A digitally Programmable Delay Element: Design and Analysis”, IEEE Trans. on VLSI Systems, vol. 11, No. 5, October 2003.
G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp , August

6. What we propose Linearization of VCDL’s transfer function
We use Current Starved DE.
Why:
Simple structure
Relatively wide range of delay regulation
How we achieve linear VCDL?
We modify the bias circuit.
We use a non-linear bias circuit which is based on the square-law characteristics of a MOS transistor in saturation.
By a cascade connection of two non-linear elements, the bias circuit and the current starved delay element, we obtain a linear transfer function (delay in terms of control voltage).

7. Delay Line Element – standard solution Cascade composition of a bias circuit and VCDL
where:
tdelay - delay time,
C - parasitic output capacitance,
Vsw ­ clock buffer (inverter) swing voltage,
Icp - charging/discharging current of C.

8. Bias circuit with reciprocal current regulation proposal

9. Schematic of a bias circuit with analytic model

10. Bias circuit HSpice simulation
Charge-discharge current variation in terms of control voltage
Relative approximation error of the reciprocal charge-discharge current variation in terms of control voltage

11. Current starved VCDL with linear delay regulation
- Complete design -
Schematic of four stage DL

12. HSpice delay line simulation – results relate to CLKout4 –
Time delay, tdelay , in term of control voltage Vctrl
Relative approximation error of time delay, tdelay , in term of control voltage Vctrl

13. DLL differential architecture
New DLL architecture with:
differential charge pump,
two low-pass filter and
nonlinear bias circuit with differential input

14. Other DLL’s parts: - dual charge pump - dynamic phase detector

15. HSpice simulation of the full DLL
CLKin
CLKout
Vctrl-
Vctrl+ UP
DOWN

16. Conclusion An implementation of DLL with a linear VCDL is proposed.
Current starved DL is used.
Linearization is achieved by modifying the bias circuit of current starved DL.
HSpice simulation results points to the fact that for 1.2 mm CMOS technology high delay linearity (error is less then 500 ps) within the full range of regulation (from 28 to 55 ns) is achieved.
Linear DL requests new DLL architecture with differential charge pump, two low-pass filter and bias circuit with differential input.

17. Q & A