1. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Overview n Why VLSI? n Moore’s Law. n Why FPGAs? n The VLSI and system design process.

2. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Why VLSI? n Integration improves the design: –lower parasitics = higher speed; –lower power; –physically smaller. n Integration reduces manufacturing cost- (almost) no manual assembly.

3. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR VLSI and you n Microprocessors: –personal computers; –microcontrollers. n DRAM/SRAM/flash. n Audio/video and other consumer systems. n Telecommunications.

4. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Moore’s Law n Gordon Moore: co-founder of Intel. n Predicted that number of transistors per chip would grow exponentially (double every 18 months). n Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

5. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Moore’s Law plot

6. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR The cost of fabrication n Current cost: $2-3 billion. n Typical fab line occupies about 1 city block, employs a few hundred people. n New fabrication processes require 6-8 month turnaround. n Most profitable period is first 18 months-2 years.

7. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Cost factors in ICs n For large-volume ICs: –packaging is largest cost; –testing is second-largest cost. n For low-volume ICs, design costs may swamp all manufacturing costs. –$10 million-$20 million.

8. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Mask cost vs. line width

9. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Field-programmable gate arrays n FPGAs are programmable logic devices: –Logic elements + interconnect. –Provide multi-level logic. LE Interconnect network LE

10. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR FPGAs and VLSI n FPGAs are standard parts: –Pre-manufactured. –Don’t worry (much) about physical design. n Custom silicon: –Tailored to your application. –Generally lower power consumption.

11. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Standard parts vs. custom n Do you build your system with an FPGA or with custom silicon? –FPGAs have shorter design cycle. –FPGAs have no manufacturing delay. –FPGAs reduce inventory. –FPGAs are slower, larger, more power-hungry.

12. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Challenges in system design n Multiple levels of abstraction: logic to CPUs. n Multiple and conflicting constraints: low cost and high performance are often at odds. n Short design time: Late products are often irrelevant.

13. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR The system design process n May be part of larger product design. n Major levels of abstraction: –specification; –architecture; –logic design; –circuit design; –layout. FPGA-based system design

14. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Dealing with complexity n Divide-and-conquer: limit the number of components you deal with at any one time. n Group several components into larger components: –transistors form gates; –gates form functional units; –functional units form processing elements; –etc.

15. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Hierarchical name n Interior view of a component: –components and wires that make it up. n Exterior view of a component = type: –body; –pins. Full adder a b cin sum cout

16. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Instantiating component types n Each instance has its own name: –add1 (type full adder) –add2 (type full adder). n Each instance is a separate copy of the type: Add1(Full adder) a b cin sum cout Add2(Full adder) a b cin sum Add1.a Add2.a

17. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR A hierarchical logic design z box1box2x

18. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Net lists and component lists n Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out n Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet

19. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Component hierarchy top i1xxxi2

20. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Hierarchical names n Typical hierarchical name: –top/i1.foo component pin

21. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Layout and its abstractions n Layout for dynamic latch:

22. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Stick diagram

23. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Transistor schematic

24. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Mixed schematic inverter

25. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Levels of abstraction n Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates + registers. n Circuits: transistor sizes for speed, power. n Layout: determines parasitics.

26. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Circuit abstraction n Continuous voltages and time:

27. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Digital abstraction n Discrete levels, discrete time:

28. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Register-transfer abstraction n Abstract components, abstract data types: + + 0010 0001 0100 0011

29. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Top-down vs. bottom-up design n Top-down design adds functional detail. –Create lower levels of abstraction from upper levels. n Bottom-up design creates abstractions from low-level behavior. n Good design needs both top-down and bottom-up efforts.

30. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Design abstractions specification behavior register- transfer logic circuit layout English Executable program Sequential machines Logic gates transistors rectangles Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns functioncost

31. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR FPGA design n FPGA manufacturer creates an FPGA fabric; system designer uses the fabric. n FPGA fabric design issues: –Study sample user designs. –Select interconnect topology. –Create logic element structures. –Design circuits, layout.

32. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Why do we care about layout? n We won’t design layout. n Layout determines: –Logic delay. –Interconnect delay. –Energy consumption. n We want to understand sources of FPGA characteristics.

33. FPGA-Based System Design: Chapter 1 Copyright  2004 Prentice Hall PTR Design validation n Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. n Forward checking: compare results of less- and more-abstract stages. n Back annotation: copy performance numbers to earlier stages.