1. EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el

2. EE141 © Digital Integrated Circuits 2nd Wires 2 The Wire schematic physical

3. EE141 © Digital Integrated Circuits 2nd Wires 3 Wire Models All-inclusive model Capacitance-only

4. EE141 © Digital Integrated Circuits 2nd Wires 4 Impact of Interconnect Parasitics  Interconnect parasitics  reduce reliability  affect performance and power consumption  Classes of parasitics  Capacitive  Resistive  Inductive

5. EE141 © Digital Integrated Circuits 2nd Wires 5 Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel Local wires dominates, but global wires are increasing. Courtesy of Intel

6. EE141 © Digital Integrated Circuits 2nd Wires 6 INTERCONNECT

7. EE141 © Digital Integrated Circuits 2nd Wires 7 Capacitance of Wire Interconnect

8. EE141 © Digital Integrated Circuits 2nd Wires 8 Capacitance: The Parallel Plate Model Total capacitance If W is substantially larger than the thickness H, parallel- plate capacitor model (also called area capacitance) just work fine:

9. EE141 © Digital Integrated Circuits 2nd Wires 9 Permittivity

10. EE141 © Digital Integrated Circuits 2nd Wires 10 Fringing Capacitance When W is not substantially larger than the thickness, fringing capacitance have to be considered. Roughly independent of W

11. EE141 © Digital Integrated Circuits 2nd Wires 11 Fringing versus Parallel Plate For larges values of (W/H), the total capacitance approaches the parallel-plate model. But for smaller values of (W/H), fringing capacitance starts to dominate. Parallel plate Measured capacitance

12. EE141 © Digital Integrated Circuits 2nd Wires 12 Capacitance: realistic case Wire Layer 1 Wire Layer 2 To first order, the total capacitance connected to a given wire does not change. The message is that not all of them terminates to ground. Inter-capacitance causes noise (cross-talk or coupling) ground

13. EE141 © Digital Integrated Circuits 2nd Wires 13 Impact of Inter-wire Capacitance When feature sizes decrease, inter-wire capacitance starts to dominate.

14. EE141 © Digital Integrated Circuits 2nd Wires 14 Wiring Capacitances (0.25  m CMOS) Rows represent the top plate, columns the bottom plate. Shaded row for fringing capacitance in aF/µm, unshaded for parallel plate capacitance (area capacitance) in aF/µm^2 smaller 40 95 85 115

15. EE141 © Digital Integrated Circuits 2nd Wires 15 Wiring Capacitances: an example Suppose that in chip with size 1cm×2cm designed in 0.25μm process, the global clock signal is routed using Metal1 with total length of 10cm and 1um wide. We can approximately compute the capacitance as follows: Area capacitance: Fringing capacitance: Total capacitance to GND: 11pF Suppose another wire of equal length is routed alongside the global clock, separated by minimum length. We can compute the inter-wire capacitance: Real situation is much more complicated: distance, shape, overlap length etc. (complex 3D analysis)

16. EE141 © Digital Integrated Circuits 2nd Wires 16 INTERCONNECT

17. EE141 © Digital Integrated Circuits 2nd Wires 17 Wire Resistance Thickness H is a technology constant.

18. EE141 © Digital Integrated Circuits 2nd Wires 18 Interconnect Resistance

19. EE141 © Digital Integrated Circuits 2nd Wires 19 Dealing with Resistance  Selective Technology Scaling  Use Better Interconnect Materials  reduce average wire-length  e.g. copper, silicide  More Interconnect Layers  reduce average wire-length

20. EE141 © Digital Integrated Circuits 2nd Wires 20 Polycide Gate MOSFET n + n + SiO 2 PolySilicon Silicide p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly A silicide is a compound material formed using silicon and a refractory metal, which is most often used in a configuration called polycide (a layer of silicide and polysilicon). This reduces the gate resistance.

21. EE141 © Digital Integrated Circuits 2nd Wires 21 Sheet Resistance

22. EE141 © Digital Integrated Circuits 2nd Wires 22 Modern Interconnect  Connection between routing layers add extra resistance, called contact resistance.  Thus the preferred routing strategy is to keep signal wires on a single layer if possible and avoid excess contacts.  Typical values: 1- 20 Ohm for contact Note: In fab, it is possible to reduce contact resistance by making the contact holes larger. But subject to current crowding (current concentrate on the perimeter)

23. EE141 © Digital Integrated Circuits 2nd Wires 23 Example: Intel 0.25 micron Process 5 metal layers

24. EE141 © Digital Integrated Circuits 2nd Wires 24 Coming issue of resistance  Resistance model presented before is usually accurate enough.  At very high frequencies, however, resistance becomes frequency dependent. High-frequency current tends to flow primarily on the surface of a conductor, with current density falling off exponentially with depth into the conductor. This is called skin effect.  Skin effect increases the resistance at high frequency  Skin effect is an issue for wide wires. The signal that is most likely to be affected is global clock signals.

25. EE141 © Digital Integrated Circuits 2nd Wires 25 INTERCONNECT

26. EE141 © Digital Integrated Circuits 2nd Wires 26 When to consider inductance  VLSI designers tend to neglect inductance effect even now  Inductance becomes important in GHz design  Main effect of inductance includes ringing, overshooting, reflections of signals and crosstalk noise due to inductive coupling  Research is going on for accurate inductive modeling and extraction

27. EE141 © Digital Integrated Circuits 2nd Wires 27 InterconnectModeling

28. EE141 © Digital Integrated Circuits 2nd Wires 28 The Lumped Model

29. EE141 © Digital Integrated Circuits 2nd Wires 29 Distributed RC: Elmore Delay model Properties: The network has a single input node All caps are between a node and GND The network does not have loops. Define shared path resistance: the resistance shared between the paths from input node to k and i

30. EE141 © Digital Integrated Circuits 2nd Wires 30 Elmore Delay model Assume that each of the nodes in the network is initially discharged to GND and a step input is applied at the source. The delay from input to node i is given by:

31. EE141 © Digital Integrated Circuits 2nd Wires 31 The Elmore Delay: RC Chain Consider a special case of RC tree network, the non- balanced RC chain.

32. EE141 © Digital Integrated Circuits 2nd Wires 32 Wire Model Assume: Wire modeled by N equal-length segments So that each segment of capacitance is C/L and resistance R/L For large values of N: Thus lumped model gives a pessimistic estimation of delay.

33. EE141 © Digital Integrated Circuits 2nd Wires 33 Step-response of RC wire as a function of time and space

34. EE141 © Digital Integrated Circuits 2nd Wires 34 RC-Models Some popular RC models used in SPICE and SPECTRE

35. EE141 © Digital Integrated Circuits 2nd Wires 35 Delay of clock: an example Suppose that in chip with size 1cm×2cm designed in 0.25um process, the global clock signal is routed using Metal1 with total length of 10cm and 1um wide. We can approximately compute the delay of the wire: With metal 1 With metal 5

36. EE141 © Digital Integrated Circuits 2nd Wires 36 Driving an RC-line

37. EE141 © Digital Integrated Circuits 2nd Wires 37 Design Rules of Thumb  rc delays should only be considered when t pRC >> t pgate of the gate itself Lcrit >>  t pgate /0.38rc  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, which is the rise (fall) time of the line t rise < RC  when not met, the change in the signal is slower than the propagation delay of the wire © MJIrwin, 2000

38. EE141 © Digital Integrated Circuits 2nd Wires 38 Future issue  Transmission Line Effects: When switching speeds of circuits becomes sufficiently fast and rise and fall times of the signal become comparable to the time of light of signal waveform across the line, as determined by the speed of light. Distributed RLC circuits should be considered. © MJIrwin, 2000