1. EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. EE415 VLSI Design 2 The Wire schematics physical

3. EE415 VLSI Design 3 Interconnect Impact on Chip

4. EE415 VLSI Design 4 Wire Models All-inclusive model Capacitance-only

5. EE415 VLSI Design 5 Impact of Interconnect Parasitics  Interconnect parasitics  reduce reliability  affect performance and power consumption  Classes of parasitics  Capacitive  Resistive  Inductive

6. EE415 VLSI Design 6 Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

7. EE415 VLSI Design 7 INTERCONNECT

8. 8 Wiring Capacitance  The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.  Wiring capacitance is growing in importance with the scaling of technology.

9. EE415 VLSI Design 9 Capacitance of Wire Interconnect

10. EE415 VLSI Design 10 Capacitance: The Parallel Plate Model

11. EE415 VLSI Design 11 Permittivity Values of Some Dielectrics 3.1 – 3.4Polyimides (organic) 2.1Teflon AF 11.7Silicon 9.5Alumina (package) 7.5Silicon nitride 5Glass epoxy (PCBs) 3.9 – 4.5Silicon dioxide 2.6 – 2.8Aromatic thermosets (SiLK) 1.5Acrogels 1Free space  di Material

12. EE415 VLSI Design 12 Fringing Capacitance

13. EE415 VLSI Design 13 Fringing versus Parallel Plate H/T W/T HTHT

14. EE415 VLSI Design 14 Sources of Interwire Capacitance C wire = C pp + C fringe + C interwire = (  di /t di )WL + (2  di )/log(t di /H) + (  di /t di )HL interwire fringe pp W W W H H H t di

15. EE415 VLSI Design 15 Impact of Interwire Capacitance

16. EE415 VLSI Design 16 Wiring Capacitances FieldActivePolyAl1Al2Al3Al4 Poly88 54 Al1304157 404754 Al213151736 25272945 Al38.99.4101541 1819202749 Al46.56.878.91535 1415 182745 Al55.25.4 6.69.11438 12 14192752 fringe in aF/  m par. plate in aF/  m 2 PolyAl1Al2Al3Al4Al5 Interwire Cap409585 115 per unit wire length in aF/  m for minimally-spaced wires

17. EE415 VLSI Design 17 Dealing with Capacitance  Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO 2  family of materials that are low-k dielectrics  must also be suitable thermally and mechanically and  compatible with (copper) interconnect  Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance  SOI (silicon on insulator) to reduce junction capacitance

18. EE415 VLSI Design 18 INTERCONNECT

19. EE415 VLSI Design 19 Wire Resistance L W H R =  L H W Sheet Resistance R  R1R1 R2R2 = =  L A = Material  (  -m) Silver (Ag)1.6 x 10 -8 Copper (Cu)1.7 x 10 -8 Gold (Au)2.2 x 10 -8 Aluminum (Al)2.7 x 10 -8 Tungsten (W)5.5 x 10 -8 Material Sheet Res. (  /  ) n, p well diffusion1000 to 1500 n+, p+ diffusion50 to 150 n+, p+ diffusion with silicide 3 to 5 polysilicon150 to 200 polysilicon with silicide 4 to 5 Aluminum0.05 to 0.1

20. EE415 VLSI Design 20 Sources of Resistance  MOS structure resistance - R on  Source and drain resistance  Contact (via) resistance  Wiring resistance Top view Drain n+Source n+ W L Poly Gate

21. EE415 VLSI Design 21 Contact Resistance  Via’s add extra resistance to a wire  keep signals wires on a single layer if possible  avoid excess contacts  using multiple vias to make the contact  Typical contact resistances, R C,  5 to 20  for metal or poly to n+, p+ diffusion and metal to poly  2 to 20  for metal to metal contacts  More pronounced with scaling since contact openings are smaller

22. EE415 VLSI Design 14: Wires22 Contacts Resistance  Use many contacts for lower R  Many small contacts for current crowding around periphery

23. EE415 VLSI Design 23 Skin Effect  At high frequency, currents tend to flow on the surface of a conductor with the current density falling off exponentially with depth into the wire H W  =  (  /(  f  )) where f is frequency  = 4  x 10 -7 H/m so the overall cross section is ~ 2(W+H)   = 2.6  m for Al at 1 GHz  The onset of skin effect is at f s - where the skin depth is equal to half the largest dimension of the wire. f s = 4  / (   (max(W,H)) 2 )  An issue for high frequency, wide (tall) wires (i.e., clocks!)

24. EE415 VLSI Design 24 Skin Effect for Different W’s  A 30% increase in resistance is observe for 20  m Al wires at 1 GHz (versus only a 1% increase for 1  m wires) 1E81E91E10 for H =.70 um

25. EE415 VLSI Design 25 Dealing with Resistance  Selective Technology Scaling  Use Better Interconnect Materials  e.g. copper, silicides  More Interconnect Layers  reduce average wire-length

26. EE415 VLSI Design 26 Polycide Gate MOSFET n + n + SiO 2 PolySilicon Silicide p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

27. EE415 VLSI Design 27 Modern Interconnect

28. EE415 VLSI Design 28 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

29. EE415 VLSI Design 29 InterconnectModeling

30. EE415 VLSI Design 30 The Lumped Model

31. EE415 VLSI Design 31 The Lumped RC-Model The Elmore Delay To model propagation delay time along a path from the source s to destination i considering the loading effect of the other nodes on the path from s to k The shared path resistance R ik The Elmore delay s

32. EE415 VLSI Design 32 The Ellmore Delay RC Chain

33. EE415 VLSI Design 33 Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

34. EE415 VLSI Design 34 The Distributed RC-line

35. EE415 VLSI Design 35 Step-response of RC wire as a function of time and space

36. EE415 VLSI Design 36 RC-Models

37. EE415 VLSI Design 37 Driving an RC-line

38. EE415 VLSI Design 38 Design Rules of Thumb  rc delays should only be considered when t pRC >> t pgate of the driving gate L crit >>  t pgate /0.38rc  rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC  otherwise, the change in the input signal is slower than the propagation delay of the wire