1. Senior Project Presentation: Designers: Shreya Prasad & Heather Smith Advisor: Dr. Vinod Prasad May 6th, 2003 Internal Hardware Design of a Microcontroller in VLSI

2. Presentation Outline Project summary Review of preliminary work Project description Functional description Subsystem block diagrams Analysis of Results Completed Tasks Improvements (if time permitted)

3. Project Summary To design some of the internal components of a microcontroller using L-EDIT. To create several delays by designing the internal 16- bit timer circuitry and 4 registers. These delays can run real time systems and interrupts. The design will also be done in VHDL code and implemented onto an FPGA board.

4. Preliminary Work http://www.play-hookey.com helped the designers with the gate-level design for the D flip-flop. http://www.stanford.edu/class/ee271 was where the designers found the transistor-level design for the XOR gate. The D flip-flop and XOR gate designs used the least number of transistors.

5. Preliminary Work D flip-flop in LEDIT

6. Preliminary Work D flip-flop plot in PSPICE

7. Project Description Functional Description User inputs: 8-bit accumulator 2-bit register controller input and 1-bit enable 2-bit clock controller input and 1-bit enable timer reset clock User outputs: 1 bit from each of the four comparators 1 bit overflow from timer

8. Project Description Functional Description Modes of operation: The user inputs 8 bits into the accumulator and 2 bits to the register controller and clock controller. The register controller specifies which register will store the 8-bit value. The clock controller specifies the period of the input clock pulse. The 16-bit timer continuously increments with the clock. The lower 8 bits input into each of the 4 comparators. They are then compared to the 8 bits stored in each register. The comparator output is logic ‘1’ when the two values are equal.

9. Project Description Block Diagram Subsystems: Clock Controller 16-bit Timer Register Controller Register Comparator

10. Project Description System Block Diagram

11. Project Description Clock Controller Subsystem Inputs: Clock (user input) Enable (user input) 2-bit Control Value (user input) Outputs: Clock (to timer and register controller subsystems)

12. Project Description Clock Controller Subsystem Block Diagram

13. Project Description Description of Clock Controller Subsystem This controls the clock pulse entering the timer subsystem. The user inputs the fastest clock pulse desired into the clock input. The subsystem can then output that pulse, or a pulse two times, four times, or eight times the period of the original pulse, into the timer subsystem. The 2-bit control value selects which pulse to output using a 4 to 1 multiplexor. The pulse periods are increased using a 3-bit counter.

14. Project Description Xilinx Design of Clock Controller Subsystem

15. Project Description LEDIT Design of Clock Controller Subsystem

16. Project Description PSpice Design of Clock Controller Subsystem

17. Project Description VHDL Design of Clock Controller Subsystem

18. Project Description 16-bit Timer Subsystem Inputs: Clock (from clock controller subsystem) Enable (user input) Reset (user input) Outputs: Lower 8 bits of timer value (to comparator subsystem) Overflow bit (external output)

19. Project Description 16-bit Timer Subsystem Block Diagram

20. Project Description Description of Timer Subsystem The enable input starts and stops the counter. It operates as a 16-bit counter. After reaching FFFFh, it sets the overflow bit high for one clock pulse and will restart at 0000h. Although only the lower 8 bits are used in the timer, having 16 bits will allow for longer delays.

21. Project Description Xilinx of Timer Subsystem

22. Project Description LEDIT of Timer Subsystem

23. Project Description PSpice of Timer Subsystem

24. Project Description VHDL Design of Timer Subsystem

25. Project Description Register Controller Subsystem Inputs: Enable (user input) Clock (from clock controller subsystem) 2-bit Control Value (user input) Outputs: Clock (to register subsystem)

26. Project Description Register Controller Subsystem Block Diagram

27. Project Description Description of Register Controller Subsystem. The 2-bit controller value specifies which of the 4 registers will receive the 8-bit accumulator value. A register will only receive the accumulator input when the register controller turns on the register’s clock. Only one register clock can be on at a time. A 2 to 4 decoder is used to select which register will receive the input clock pulse.

28. Project Description Xilinx of Register Controller Subsystem

29. Project Description LEDIT of Register Controller Subsystem

30. Project Description PSpice of Register Controller Subsystem

31. Project Description VHDL Design of Register Controller Subsystem

32. Project Description Register Subsystem Inputs: 8-bit Accumulator Value (from accumulator) Clock (from register controller) Outputs: 8-bit Register Value (to comparator subsystem)

33. Project Description Register Subsystem Block Diagram

34. Project Description Description of Register Subsystem Each register will consist of 8 D flip-flops, which will store the register value. A register stores the accumulator value only when the controller turns on its clock. Otherwise, the register will hold its previous value until this value is written over with a new value from the accumulator.

35. Project Description LEDIT of Register Subsystem

36. Project Description PSpice of Register Subsystem

37. Project Description VHDL Code for Register Subsystem

38. Project Description Comparator Subsystem Inputs: 8-bit Register Value (from register subsystem) Lower 8-bit Timer Value (from timer subsystem) Outputs: 1-bit Compared Value (external output)

39. Project Description Comparator Subsystem Block Diagram

40. Project Description Description of Comparator Subsystem There are 4 comparators, 1 for each register. The 8-bit value from each register is compared to the lower 8 bits of the timer. If the two inputs are the same, the output is logic ‘1’. Otherwise, the output is logic ‘0’.

41. Project Description Xilinx of Comparator Subsystem

42. Project Description LEDIT of Comparator Subsystem

43. Project Description PSpice of Comparator Subsystem

44. Project Description VHDL Code for Comparator Subsystem

45. Analysis of Results Xilinx Design of Complete System Each subsystem was designed and tested in a separate Xilinx file. Macros were used to turn each subsystem file into a single block showing only the subsystem’s inputs and outputs. The subsystem blocks were then combined together and tested.

46. Analysis of Results Xilinx Design of Complete System

47. Analysis of Results L-Edit Design of Complete System Each subsystem was designed and tested in a separate L-Edit file. Creating an instance for each subsystem allowed the designers to combine the subsystems into a single file. Once the subsystems were connected, an extract file was created to test the L-Edit design in Pspice. The design contained 2,522 transistors.

48. Analysis of Results L-Edit Design of Complete System

49. Analysis of Results PSpice Design of Complete System Each subsystem’s reset was set high to initialize the system. Various clock pulse periods were set up in the extract file to allow the accumulator to take values into the appropriate register. Register values were chosen to match timer values. The outputs of the comparator subsystem were checked to see if they went high when the register value was equal to the lower 8-bit timer value.

50. Analysis of Results PSpice Design of Complete System

51. Analysis of Results PSpice Design of Complete System compare bit 2 goes high when timer and register 2 are “00001000”

52. Analysis of Results PSpice Design of Complete System compare bit 3 goes high when timer and register 3 are “00000011” and “00000111”

53. Analysis of Results VHDL Design of Complete System All of the individual VHDL files were compiled and placed into one project. A system file was written to incorporate all the subsystems. A test bench was also written for the system. The comparator outputs were checked.

54. Analysis of Results VHDL Design of Complete System

55. Analysis of Results VHDL Design of Test bench for Complete System

56. Analysis of Results VHDL Design of Complete System

57. Completed Tasks

58. Improvements (if time permitted) The timer design included the output compare mode; however, the input capture mode could also be designed. An input capture interrupt would be set high. The 16-bit timer value would be “captured” by storing it in a 16-bit register. An instruction register (IR) subsystem could also have been added. Binary codes for various instructions (move, store, add, etc.) would be decoded in the instruction register.

59. Questions?